US 6,321,301 B1Granted

Cache memory device with prefetch function and method for asynchronously renewing tag addresses and data during cache miss states

AssigneeIndustrial Technology Research Institute

InventorsMing-Fen Lin, Chung-Ching Chen, Ming-Tsan Kao

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Abstract

A cache device and a method of using the same for data accesses according to the invention. Particularly, the cache device has a prefetch queue comparing circuit which comprises a cache hit/miss judging circuit, an address queue register and a prefetch condition judging circuit. The cache hit/miss judging circuit is used to judge whether a currently-read address coming from a bus is of cache hit or cache miss, wherein the address consists of an index address and a tag address. The address queue register directly stores the index address of the currently-read address plus a corresponding first one-bit flag signal if the cache hit/miss judging circuit judges that the currently-read address is of cache hit. The prefetch condition judging circuit is used to judge whether the index address of the currently-read address is the same as any index addresses already stored in the address queue register if the cache hit/miss judging circuit judges that the currently-read address is of cache miss. If the index address is not the same as any index address still stored in the address queue register, a corresponding tag address and data originally stored in a tag memory and a data memory, respectively are renewed in an asynchronous way.

Claims6

Dependent claims

A cache device, electrically coupled to a primary memory through a bus, comprising:

a data memory for storing data at corresponding index addresses;
a tag memory for storing tag addresses at the corresponding index addresses;
and
a cache control circuit having a prefetch queue comparing circuit which comprises:
a cache hit/miss judging circuit for judging whether a currently-read address coming from the bus is of cache hit or cache miss, wherein the address consists of an index address and a tag address;
an address queue register for directly storing the index address of the currently-read address plus a corresponding first one-bit flag signal output from the cache hit/miss judging circuit if the cache hit/miss judging circuit judges that the currently-read address is of cache hit, wherein the address queue register always continuously outputs index addresses already stored therein in first in-first out order to the data memory for data accesses;
and
a prefetch condition judging circuit for judging whether the index address of the currently-read address is the same as any index addresses already stored in the address queue register if the cache hit/miss judging circuit judges that the currently-read address is of cache miss;
wherein an original tag address stored at the same index address in the tag memory is replaced with the tag address of the currently-read address with the control of the cache control circuit, and then the index address plus a corresponding second one-bit flag signal output from the cache hit/miss judging circuit are stored in the address queue register when the index address is not the same as any index addresses still stored in the address queue register, and according to the second one-bit flag signal, original data stored at the same index address in the data memory are replaced with required data stored at the same currently-read address in the primary memory, and then the second one-bit flag signal is changed into the first one-bit flag signal with the control of the cache control circuit.

6 more elements

A method of using a cache device for data accesses, wherein the cache device electrically coupled to a primary memory through a bus includes a data memory, a tag memory and a prefetch queue comparing circuit which includes a cache hit/miss judging circuit, an address queue register and a prefetch condition judging circuit, comprising the following steps:

(a) judging whether a currently-read address coming from the bus is of cache hit or cache miss by the cache hit/miss judging circuit, wherein the address consists of an index address and a tag address;
(b) directly storing the index address of the currently-read address plus a corresponding first one-bit flag signal output from the cache hit/miss judging circuit in the address queue register if the cache hit/miss judging circuit judges that the currently-read address is of cache hit, wherein the address queue register always continuously outputs index addresses already stored therein in first in-first out order to the data memory for data accesses;
(c) judging whether the index address of the currently-read address is the same as any index addresses already stored in the address queue register by the prefetch condition judging circuit if the cache hit/miss judging circuit judges that the currently-read address is of cache miss;
(d) replacing an original tag address stored at the same index address in the tag memory with the tag address of the currently-read address when the index address is not the same as any index addresses still stored in the address queue register;
(e) storing the index address plus a corresponding second one-bit flag signal output from the cache hit/miss judging circuit in the address queue register after step (d);
(f) replacing original data stored at the same index address in the data memory with required data stored at the same currently-read address in the primary memory after step (e);
and
(g) changing the second one-bit flag signal into the first one-bit flag signal after step (f).

5 more elements

Dependencies are inferred from the claim text.