Apparatus and method for dynamically reconfigurable timed flushing of a queue of coalescing write buffers

A method for dynamically reconfigurable timed flushing of a plurality of coalescing write buffers, comprising:

• comparing an address of a buffered write operation against line addresses of allocated coalescing write buffers to determine whether there is a match;
• if there is a match;
• writing at least a byte of data to corresponding byte locations in the allocated coalescing write buffer whose line address matched with the address of the buffered write operation;
• setting byte valid bits corresponding to said byte locations;
• resetting a counter associated with the allocated coalescing write buffer and employed to determine whether a time-out period has expired for the allocated coalescing write buffer;
• and
• activating a flip-flop input associated with the allocated coalescing write buffer for determining a least recently written to allocated coalescing write buffer;
• and
• if there is no match;
• newly allocating an unallocated coalescing write buffer to the address of the buffered write operation;
• updating a state of said newly allocated coalescing write buffer to indicate its allocation;
• changing the time-out periods for counters associated with all allocated coalescing write buffers;
• writing at least a byte of data to corresponding byte locations in the newly allocated coalescing write buffer;
• setting byte valid bits corresponding to said byte locations;
• resetting a counter associated with the newly allocated coalescing write buffer and employed to determine whether a time-out period has expired for the newly allocated coalescing write buffer;
• and
• activating a flip-flop input associated with the newly allocated coalescing write buffer for determining a least recently written to allocated coalescing write buffer.

A write buffer unit configured to operate in conjunction with a cache memory in a microprocessor system, said write buffer unit comprising:

• a controller;
• a plurality of coalescing write buffers coupled to said controller;
• means, including said controller, for generating a time-out period inversely related to a number totaling the allocated coalescing write buffers;
• means, including said controller, for determining a least recently written to allocated coalescing write buffer;
• and
• means, including said controller, for generating a signal to flush said least recently written to allocated coalescing write buffer when a period of time initiated by a most recent write to one of said allocated coalescing write buffers exceeds said time-out period.

An apparatus for dynamically reconfigurable timed flushing of a plurality of coalescing write buffers, comprising:

• at least one time-out generator logic, coupled to said plurality of coalescing write buffers and configured to decrement a time-out period when a coalescing write buffer is allocated and to increment the time-out period when said coalescing write buffer is deallocated;
• an LRW logic device, coupled to said at least one time-out generator logic and configured to determine a least recently written to allocated coalescing write buffer;
• and
• a control logic, coupled to said LRW logic device and to said at least one time-out generator logic, said control logic configured to generate a signal to flush said least recently written to allocated coalescing write buffer when a period of time initiated by a most recent write to one of said allocated coalescing write buffers exceeds said time-out period.