Method and apparatus for integrated circuit design verification

A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform a method for verifying a design of an integrated circuit, the integrated circuit having a set of functional constraints, the method comprising:

• generating a binary decision diagram (BDD) based on the set of functional constraints, the binary decision diagram comprising a plurality of nodes, each of the plurality of nodes having at least one branch, wherein each of the plurality of nodes represents an input signal used in the integrated circuit, wherein each input signal has an associated weight;
• reordering the binary decision diagram;
• assigning a node weight to each of the plurality of nodes based on the associated weight;
• assigning a branching probability to each branch of each of the plurality of nodes based on the logic data structure and the associated weight;
• generating a first set of simulation inputs based on the logic data structure and branching probabilities;
• generating a simulation control program for simulating the design of the integrated circuit;
• initializing simulation of the design of the integrated circuit;
• simulating the design of the integrated circuit;
• determining at least one state condition of the design of the integrated circuit;
• and
• adjusting branching probabilities in response to the at least one state condition.

A computer storage medium readable by a computer and storing a program of instructions executable by the computer to implement a circuit design verification tool, the circuit design verification tool comprising:

• a logic compiler, the logic compiler receiving a design file, a set of design constraints and a set of weights, the logic compiler building a logic data structure that incorporates state information to represent an input space which satisfies the set of design constraints;
• a control program generator for generating a control program, the control program generator receiving the logic data structure from the logic compiler, the control program generator generating a simulation control program based on the logic data structure and assigning branching probabilities to the logic data structure corresponding to the set of weights;
• and
• a simulation program code means, the simulation program code means simulating a circuit design in response to receiving the simulation control program from the control program generator, the simulation program code means providing a current state condition to the control program generator which the control program generator uses to adjust the branching probabilities.

An article of manufacture comprising:

• a computer usable medium having computer readable program code means embodied therein for circuit design verification, the computer readable program code means in said article of manufacture comprising:
• a first computer readable program code means for receiving design file information and design constraint information;
• a second computer readable program code means for generating a weighted binary decision diagram (BDD) data structure, the weighted BDD having a plurality of binary nodes corresponding to functional signals within a circuit, each of the plurality of binary nodes having two edges;
• a third computer readable program code means for generating simulation controls based on the weighted BDD, the third means assigning an associated branching probability to each of the two edges;
• and
• a fourth computer readable program code means for providing at least one current state condition within the weighted binary decision diagram data structure to the third computer program code means, the third computer readable program code means adjusting branching probability in response to the at least one current state condition.

A circuit design verifier stored on a computer readable medium, the circuit design verifier for verifying a design of an integrated circuit having a set of functional constraints, comprising:

• computer readable first program code means for generating a logic data structure based on the set of functional constraints, the logic data structure comprising a plurality of nodes, wherein each of the plurality of nodes represents an input signal to the integrated circuit, wherein each of the plurality of input signals has a associated weight;
• computer readable second program code means for assigning a probability to each of the plurality of nodes based on the associated weight;
• computer readable third program code means for generating a first set of simulation inputs based on the logic data structure and probabilities;
• and
• computer readable fourth program code means for controlling simulation design of the integrated circuit using the first set of simulation inputs and at least a second subsequent set of simulation inputs derived from at least one state condition determined after using the first set of simulation inputs.