Estimation system of LSI power consumption

An estimation system of LSI power consumption, at which estimates the power consumption of a new designing LSI chip having core circuitry, comprising:

• an I/O part estimating section which estimates I/O part power of said new designing LSI chip and I/O part power of the existing original LSI chip having the core of the same function that the core circuitry of said new designing LSI chip has, based on the outside specifications required by the application of the LSI chip;
• a data base of the ratio of each function which stores the ratio of the number of FF/gates and the ratio of clock power/logic power in the kinds of functions;
• a core circuitry part estimating section which calculates the core power of the original LSI chip subtracting said I/O part power of the original LSI chip calculated at said I/O part estimating section from the known total power of the original LSI chip and converts voltage, process and frequency from the core power of the original LSI chip to the core circuitry power of the new designing LSI chip and estimates the core circuitry power of the new designing LSI chip;
• a modifiable circuitry part estimating section which calculates the ratio of the number of FF/gates and the ratio of clock power/logic power referring to said data base of the ratio of each function from the kinds of functions and calculates clock system power based on the ratio of the number of FF (flip-flop)/gates, voltage, frequency, the number of gates, unit capacity and clock structure and calculates logic system power using the ratio of the clock/logic power and calculates the modifiable circuitry part power summing up the clock system power and the logic system power;
• and
• an LSI chip power calculating section which calculates the power of the new designing LSI chip summing up the I/O part power calculated at said I/O part estimating section and the core circuitry power calculated at said core circuitry part estimating section and the modifiable circuitry part power calculated at said modifiable circuitry part estimating section.

An estimation method of LSI power consumption, at which estimates the power consumption of a new LSI chip, comprising:

• an I/O part estimating method which estimates I/O part power of an LSI chip based on the outside specifications required by the application of the LSI chip;
• a modifiable circuitry part estimating method which obtains the ratio of the number of FF/gates and the ratio of clock power/logic power referring to the data base of the ratio of each function which stores the ratio of the number of FF/gates and the ratio of clock power/logic power in the kinds of functions and calculates clock system power based on the ratio of the number of FF/gates, voltage, frequency, the number of gates, unit capacity and clock structure and calculates logic system power using the ratio of the clock/logic power and calculates modifiable circuitry part power summing up the clock system power and the logic system power;
• and
• an LSI chip power calculating method which calculates the power of the new LSI chip summing up the I/O part power calculated at said I/O part estimating method and the modifiable circuitry part power calculated at said modifiable circuitry part estimating method.

An estimation method of LSI power consumption, at which estimates the power consumption of a new LSI chip having core circuitry, comprising:

• an I/O part estimating method which estimates I/O part power of said new LSI chip and I/O part power of the existing original LSI chip having the core of the same function that the core circuitry of said new LSI chip has, based on the outside specifications required by the application of the LSI chip;
• a core circuitry part estimating method which calculates the core power of the original LSI chip subtracting said I/O part power of the original LSI chip calculated at said I/O part estimating method from the known total power of the original LSI chip and converts voltage, process and frequency from the core power of the original LSI chip to the core circuitry power of the new LSI chip and estimates the core circuitry power of the new LSI chip;
• a modifiable circuitry part estimating method which obtains the ratio of the number of FF/gates and the ratio of clock power/logic power referring to the data base of the ratio of each function which stores the ratio of the number of FF/gates and the ratio of clock power/logic power in the kinds of functions and calculates clock system power based on the ratio of the number of FF/gates, voltage, frequency, the number of gates, unit capacity and clock structure and calculates logic system power using the ratio of the clock/logic power and calculates the modifiable circuitry part power summing up the clock system power and the logic system power;
• and
• an LSI chip power calculating method which calculates the power of the new LSI chip summing up the I/O part power calculated at said I/O part estimating method and the core circuitry power calculated at said core circuitry part estimating method and the modifiable circuitry part power calculated at said modifiable circuitry part estimating method.

Recording media recording programs to implement an estimation of LSI power consumption, comprising:

• an I/O part estimation program which estimates I/O part power of an LSI chip based on the outside specifications required by the application of the LSI chip;
• a modifiable circuitry part estimation program which obtains the ratio of the number of FF/gates and the ratio of clock power/logic power referring to the data base of the ratio of each function which stores the ratio of the number of FF/gates and the ratio of clock power/logic power in the kinds of functions and calculates clock system power based on the ratio of the number of FF/gates, voltage, frequency, the number of gates, unit capacity and clock structure and calculates logic system power using the ratio of the clock/logic power and calculates modifiable circuitry part power summing up the clock system power and the logic system power;
• and
• an LSI chip power calculation program which calculates the power of the new LSI chip summing up the I/O part power calculated at said I/O part estimation program and the modifiable circuitry part power calculated at said modifiable circuitry part estimation program.

Recording media recording programs to implement an estimation of LSI power consumption, comprising:

• an I/O part estimation program which estimates I/O part power of said new LSI chip and I/O part power of the existing original LSI chip having the core of the same function that the core circuitry of said new LSI chip has, based on the outside specifications required by the application of the LSI chip;
• a core circuitry part estimation program which calculates the core power of the original LSI chip subtracting said I/O part power of the original LSI chip calculated at said I/O part estimation program from the known total power of the original LSI chip and converts voltage, process and frequency from the core power of the original LSI chip to the core circuitry power of the new LSI chip and estimates the core circuitry power of the new LSI chip;
• a modifiable circuitry part estimation program which obtains the ratio of the number of FF/gates and the ratio of clock power/logic power referring to the data base of the ratio of each function which stores the ratio of the number of FF/gates and the ratio of clock power/logic power in the kinds of functions and calculates clock system power based on the ratio of the number of FF/gates, voltage, frequency, the number of gates, unit capacity and clock structure and calculates logic system power using the ratio of the clock/logic power and calculates the modifiable circuitry part power summing up the clock system power and the logic system power;
• and
• an LSI chip power calculation program which calculates the power of the new LSI chip summing up the I/O part power calculated at said I/O part estimation program and the core circuitry power calculated at said core circuitry part estimation program and the modifiable circuitry part power calculated at said modifiable circuitry part estimation program.