US 6,321,184 B1 · Reduction of arbitrary L1-L2 circuits for enhanced verification

Abstract

A method of generating a digital circuit model that has fewer latches than the circuit being modeled. Initially, a determination of whether the digital circuit is reducible is made. The digital circuit suitably includes one or more primary inputs, one or more primary outputs, and a plurality of latches comprised of a level one (L1) latch set and a level two (L2) latch set wherein the latch sets may or may not lack one-to-one correspondence. After determining that the digital circuit is reducible, at least one of the latches is replaced with combinational logic thereby reducing the latch count of the digital circuit model. Preferably, the determination of whether the digital circuit is reducible is accomplished by determining whether (a) the transitive fanin of the L1 latch set includes only the primary inputs of the digital circuit and outputs of the L2 latch set, (b) the transitive fanout of the L1 latch set includes only inputs to the L2 latch set, (c) the transitive fanin of the L2 latch set includes only out puts from the L1 latch set, and (d) the transitive fanout of the L2 latch set includes only the primary outputs of the digital circuit and inputs to the L1 latch set. In the preferred embodiment, the replacement of the latch(es) is made by identifying either the latch set with the higher latch count as the replaceable latch set and replacing each its latches with combinational logic such as a simple wire or a multiplexed useful for retaining an initial condition of the digital circuit in the circuit model.

Claims19

Dependent claims

A method of reducing latch count in a model of a digital circuit, said method comprising:

determining whether a model of said digital circuit is reducible, said digital circuit model comprising primary inputs, primary outputs, and a plurality of latches comprised of level one (L1) and level two (L2) latch sets wherein said L1 and L2 latch sets lack one-to-one correspondence;
replacing at least one of said plurality of latches with combinational logic in said model whereby said model comprises fewer latches than said digital circuit and
using said reduced latch count model to simulate said digital circuit.

A storage medium configured with computer instructions for reducing latch count in a model of a digital circuit, said computer instructions, when executed, perform the method comprising:

determining whether said digital circuit model is reducible, said digital circuit comprising, primary inputs, primary outputs, and a plurality of latches comprised of a level one (L1) latch set and a level two (L2) latch set wherein said L1 and L2 latch sets lack one-to-one correspondence;
identifying a replaceable latch set from the group consisting of said L1 latch set and said L2 latch set if said digital circuit model is reducible;
replacing, in said model, each latch of said replaceable latch set with combinational logic whereby a latch count of said model is less than a latch count of said digital circuit:
and
using said reduced latch count model to simulate said digital circuit.

2 more elements

Dependencies are inferred from the claim text.

Reduction of arbitrary L1-L2 circuits for enhanced verification

Life of this patent

Reduction of arbitrary L1-L2 circuits for enhanced verification

Life of this patent

Abstract

Claims19