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US 6,320,964 B1Granted
Cryptographic accelerator
AssigneeIntel Corporation
InventorRoy Callum
Life of this patent
Estimating the term…
Abstract
A cryptographic accelerator for handling instruction-intensive bit permutations. The cryptographic accelerator comprises a selector and a plurality of buses coupled to the selector. Herein, at least one of the plurality of buses includes signal lines routed to perform a bit permutation operation incoming data. The bit permutation operation is one of a plurality of operations associated with a symmetric key function.
Claims13
A cryptographic accelerator comprising:
- a select circuit;
- and
- a plurality of buses coupled to the select circuit, of the plurality of buses include
- a first bus having signal lines arranged to perform an initial permutation operation in accordance with a symmetric key function,
- a second bus having signal lines arranged to perform a first permuted choice operation in accordance with the symmetric key function in order to modify contents of an original key by producing a first data block and a second data block,
- a third bus having signal lines arranged to perform a second permuted choice operation in accordance with the symmetric key function in order to modify the first data block and the second data block to produce a key block, the key block being one of a plurality of keys used to iteratively encrypt incoming information, and
- a fourth bus having signal lines arranged to perform a one-bit right shift on a bit representation of the incoming information.
4 more elements
An electronic system comprising:
- a memory controller;
- and
- a processor coupled to the memory controller, the processor including a cryptographic accelerator having
- a selector, and
- a plurality of buses coupled to the selector, the plurality of buses exclusively performing bit permutation operations on incoming information to rearrange bit ordering of the incoming information in accordance with a symmetric key function, the plurality of buses includes
- a first bus including signal lines arranged to perform an initial permutation operation in accordance with the symmetric key function,
- a second bus including signal lines arranged to perform a first permuted choice operation in accordance with the symmetric key function in order to modify contents of an original key by producing a first data block and a second data block, and
- a third bus including signal lines arranged to perform a second permuted choice operation in accordance with the symmetric key function in order to modify the first data block and the second data block to produce a key block, the key block being one of a plurality of keys used to iteratively encrypt the incoming information.
5 more elements
Dependencies are inferred from the claim text.