OFDM symbol synchronization

Apparatus for processing a signal which comprises a succession of symbol periods TT each consisting of an active symbol period TS and a guard interval TG, the apparatus comprising:

• an input for receiving an input signal Y;
• a delay coupled to the input for providing a delayed signal X from the input signal Y, the delayed signal being delayed by a time period equal to the active symbol period TS;
• complex product forming circuitry coupled to the input and the delay for receiving the input signal Y from the input and the delayed signal X from the delay and for forming a complex product which is one of XY* and X*Y, being the product of one of the input signal and the delayed signal, with the complex conjugate of the other of the input signal and the delayed signal and for outputting a complex product signal related to the complex produce and comprising a succession of pulses having real and imaginary components, one pulse for each symbol period;
• and
• a magnitude detector coupled to the complex product forming circuitry for determining which of the real and imaginary components of the complex product signal has the larger magnitude and selecting the larger one as an output.

Apparatus for synchronizing with a signal which comprises a succession of symbol periods TT each consisting of an active symbol period TS and a guard interval T, the apparatus comprising:

• means for forming a complex signal from the received signal;
• clock means for generating clock signals for use in forming the complex signal;
• means for forming symbol pulses from the input signal;
• synchronization means coupled to receive the symbol pulses and the clock signals, the sychronization means including:
• a first recirculating counter for counting clock signals and for providing a count representative thereof;
• register means for receiving the count from the first recirculating counter and for holding the count at a time determined by the receipt of the symbol pulses, the clock means being controlled by the held count;
• an OR gate having a first input coupled to receive the incoming symbol pulses and a second input, and providing an output;
• a second recirculating counter coupled to receive the output of the OR gate, the second recirculating counter providing an output to the second input of the OR gate;
• and
• an AND gate coupled to receive the outputs of the first recirculating counter and the second recirculating counter to provide synchronized symbol pulses.

Apparatus for processing a signal which comprises a succession of symbol periods TT at a defined symbol frequency, each symbol period consisting of an active symbol period TS and a guard interval TG, the apparatus comprising:

• an input for receiving an input signal Y;
• a delay coupled to the input for providing a delayed signal X from the input signal Y, the delayed signal being delayed by a time period equal to the active symbol period TS;
• means for forming symbol pulses from the input signal;
• complex product forming circuitry coupled to the input and the delay for receiving the input signal Y from the input and the delayed signal X from the delay and for forming a complex product which is one of XY* and X*Y, being the product of one of the input signal and the delayed signal with the complex conjugate of the other of the input signal and the delayed signal, and for outputting a complex product signal related to the complex product and comprising a succession of pulses having real and imaginary components, one pulse for each symbol period;
• a high-pass filter coupled to the complex product forming circuitry for high-pass filtering the complex product signal to suppress frequencies substantially below the symbol frequency;
• clock means for generating clock signals for use in extracting the information from the input signal;
• a magnitude detector coupled to the complex product forming circuitry for determining which of the real and imaginary components of the complex product signal has the larger magnitude and selecting the larger one to control synchronization of the clock means;
• and
• synchronization means coupled to receive the symbol pulses and the clock signals, the synchronization means including:
• a first recirculating counter for counting clock signals and for providing a count representative thereof;
• register means for receiving the count from the first recirculating counter and for holding the count at a time determined by the receipt of the symbol pulses, the clock means being controlled by the held count;
• an OR gate having a first input coupled to receive the incoming symbol pulses and a second input, and providing an output;
• a second recirculating counter coupled to receive the output of the OR gate, the second recirculating counter providing an output to the second input of the OR gate;
• and
• an AND gate coupled to receive the outputs of the first recirculating counter and the second recirculating counter to provide synchronized symbol pulses.