Semiconductor device reconciling different timing signals
AssigneeFujitsu Limited
InventorsHiroyoshi Tomita, Tatsuya Kanda
Life of this patent
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Abstract
A semiconductor device which receives addresses in synchronism with a clock signal and receives data in synchronism with a strobe signal includes address-latch circuits, a first control circuit which selects one of the address-latch circuits in sequence in response to the clock signal, and controls the selected one of the address-latch circuits to latch a corresponding one of the addresses in response to the clock signal, and a second control circuit which selects one of the address-latch circuits in sequence in response to the strobe signal, and controls the selected one of the address-latch circuits to output a corresponding one of the addresses in response to the strobe signal.
Claims6
A memory circuit, comprising:
- an address-input circuit which latches address signals in response to a clock signal, and outputs the address signals in response to the clock signal, said address-input circuit includes a delay circuit which operates in response to the clock signal;
- a data-input circuit which latches data signals in response to a strobe signal, and outputs the data signals in response to the clock signal;
- an internal circuit which writes the data signals supplied from the data-input circuit in memory cells indicated by the address signals supplied from the address-input circuit;
- and
- a bypass circuit provided in parallel to said delay circuit, wherein the address signals pass through the bypass circuit and bypass said delay circuit in a data-read mode.
A memory circuit, comprising:
- an address-input circuit which latches address signals in response to a clock signal, and outputs the address signals in response to a strobe signal, the address-input circuit includes a delay circuit which operates in response to a clock signal;
- a data-input circuit which latches data signals in response to a strobe signal, and outputs the data signals in response to the strobe signal;
- an internal circuit which writes the data signals supplied from the data-input circuit in memory cells indicated by the address signals supplied from the address-input circuit;
- and
- a bypass circuit provided in parallel to said delay circuit, wherein the address signals pass through the bypass circuit and bypass said delay circuit in a data-read mode.
Dependencies are inferred from the claim text.