Semiconductor storage device, and method for generating timing of signal for activating internal circuit thereof

A semiconductor storage device comprising:

• means for determining a pulse width by using an external clock signal when a READ command is input as a start point and thereby, making a sense-amplifier activation signal or latch capture signal of a synchronous mask ROM synchronize with activation or inactivation of a clock signal after cycles corresponding to the number of clocks of a set latency to generate timing;
• and a latency calculation circuit, a timing generation circuit, a plurality of cells, a plurality of sense amplifiers, a plurality of latches, and an output buffer, wherein:
• said latency calculation circuit has means for receiving a plurality of signals for determining the latency, an internal clock signal generated from said external clock, and a signal generated when the READ command is input and outputting a plurality of signals to said timing generation circuit;
• said timing generation circuit has means for receiving a pulse signal generated when the READ command is input and a reset signal, outputting said sense-amplifier activation signal to said sense amplifiers, and outputting said latch capture signal to said latches;
• said latches have means for inputting outputs of said latches to said output buffer by selectively conducting said outputs in accordance with select signals;
• and
• said output buffer has means for outputting said data input from said latches synchronously with said internal clock signal synchronizing with said external clock.

A method for generating the timing of a signal for activating an internal circuit of a semiconductor storage device, configured by means for determining a pulse width by using an external clock signal when a READ command is input as a start point and thereby, making a sense-amplifier activation signal or latch capture signal of a synchronous mask ROM synchronize with activation or inactivation of a clock signal after cycles corresponding to the number of clocks of a set latency to generate timing;

• and a latency calculation circuit, a timing generation circuit, a plurality of cells, a plurality of sense amplifiers, a plurality of latches, and an output buffer, in which:
• said latency calculation circuit has means for receiving a plurality of signals for determining said latency, an internal clock signal generated from said external clock, and a signal generated when said READ command is input and outputting a plurality of signals to said timing generation circuit;
• said timing generation circuit has means for receiving a pulse signal generated when said READ command is input and a reset signal, outputting said sense-amplifier activation signal to said sense amplifiers, and outputting said latch capture signal to said latches;
• said plurality of latches have means for inputting outputs of said latches to said output buffer by selectively conducting said outputs in accordance with select signals;
• and
• said output buffer has means for outputting said data input from said latches synchronously with said internal clock signal synchronizing with said external clock, said method comprising the steps of:
• generating a pulse signal by inputting a READ command to said external clock;
• generating said sense-amplifier activating signal and said latch capture signal through said latency calculation circuit and said timing generation circuit respectively synchronizing an internal clock signal generated from said external clock in accordance with said pulse signal;
• activating said sense amplifiers in accordance with said sense-amplifier activating signal, and thereby reading and outputting the data for the cells;
• activating said latches in accordance with said latch capture signal and thereby latching said data output from said sense amplifiers;
• inputting said data latched in a latency period to said output buffer depending on which one of select signals for respectively determining a burst output is selected;
• and
• outputting said data input from said latches to said output buffer synchronously with the internal clock signal.