Tri-stating address input circuit

A dynamic random access memory (DRAM), comprising:

• a plurality of address buffers, each buffer including:
• a tri-state input stage, comprising:
• a first transistor operatively coupled to an enablement complement signal;
• a second transistor operatively coupled to a data input and the first transistor;
• a third transistor operatively coupled to the data input and the second transistor;
• and
• a fourth transistor operatively coupled to a n enablement signal and the third transistor;
• and
• an address output latch operatively coupled to the tri-state input stage, the address out put latch including:
• a first inverter;
• at least one second inverter operatively coupled to the first inverter;
• and
• a multiplexor operatively coupled in parallel with both the first and the at least one second inverter, the multiplexor comprising first and second transistors in parallel.

A dynamic random access memory (DRAM), comprising:

• at least one address buffer, including:
• a tri-state input stage, comprising:
• a first P channel metal oxide semiconductor (PMOS) transistor operatively coupled to an enablement complement signal;
• a second PMOS transistor operatively coupled to a data input and the first PMOS transistor;
• a third N channel metal oxide semiconductor (NMOS) transistor operatively coupled to the data input and to the second PMOS transistor to provide an output of the tri-state input stage;
• and
• a fourth NMOS transistor operatively coupled to an enablement signal and the third NMOS transistor;
• and
• an address output latch operatively coupled to the output of the tri-state input stage, the address output latch including;
• at least one inverter operatively coupled to the second and third transistors of the tri-state input stage;
• and
• a multiplexor operatively coupled in parallel with the at least one inverter, the multiplexor comprising an n-channel transistor and a p-channel transistor in parallel and having their respective gates coupled to complementary control signals and operable for providing a controllable feedback path from an output to an input of the address output latch.

A dynamic random access memory (DRAM), comprising:

• at least one address buffer, including:
• a tri-state input stage, comprising:
• a first transistor operatively coupled to an enablement complement signal;
• a second transistor operatively coupled to a data input and the first transistor;
• a third transistor operatively coupled to the data input and the second transistor;
• and
• a fourth transistor operatively coupled to an enablement signal and the third transistor;
• and
• an address output latch operatively coupled to the second and third transistors of the tri-state input stage, the address output latch including:
• a first gate operatively coupled to the tri-state input stage;
• at least one second gate operatively coupled to the first gate;
• and
• a switch operatively coupled in parallel with both the first and the at least one second gate to selectively latch a signal;
• an address decoder operatively coupled to the at least one second gate;
• an address controller operatively coupled to the address decoder;
• a memory array operatively coupled to the address decoder;
• and
• an input/output circuit operatively coupled to the address decoder, address controller, and memory array.

A dynamic random access memory (DRAM), comprising:

• a plurality of address buffers, each address buffer including:
• a tri-state input stage, comprising:
• a first transistor operatively coupled to an enablement complement signal;
• a second transistor operatively coupled to a data input and the first transistor;
• a third transistor operatively coupled to the data input and the second transistor;
• and
• a fourth transistor operatively coupled to an enablement signal and the third transistor;
• and
• an address output latch operatively coupled to the tri-state input stage, the address output latch including:
• a first inverter operatively coupled to the second and third transistors of the tri-state input stage;
• at least one second inverter operatively coupled to the first inverter;
• and
• a multiplexor operatively coupled in parallel with both the first and the at least one second inverter;
• an address decoder operatively coupled to the at least one second inverter of the output latch of each of the plurality of address buffers;
• an address controller operatively coupled to the address decoder;
• a memory array operatively coupled to the address decoder;
• and
• an input/output circuit operatively coupled to the address decoder, address controller, and memory array.

A dynamic random access memory (DRAM), comprising:

• at least one address buffer, including:
• a tri-state input stage, comprising:
• a first transistor operatively coupled to an enablement complement signal;
• a second transistor operatively coupled to a data input and the first transistor;
• a third transistor operatively coupled to the data input and the second transistor;
• and
• a fourth transistor operatively coupled to an enablement signal and the third transistor;
• and
• an address output latch operatively coupled to the tri-state input stage, the address output latch including:
• a first inverter;
• at least one second inverter operatively coupled to the first inverter;
• and
• a multiplexor operatively coupled in parallel with both the first and the at least one second inverter, the multiplexor comprising first and second transistors in parallel;
• an address decoder operatively coupled to the at least one second inverter;
• an address controller operatively coupled to the address decoder;
• a memory array operatively coupled to the address decoder;
• and
• an input/output circuit operatively coupled to the address decoder, address controller, and memory array.

A dynamic random access memory (DRAM), comprising:

• at least one address buffer, including:
• a tri-state input stage, comprising:
• a first transistor operatively coupled to an enablement complement signal;
• a second transistor operatively coupled to a data input and the first transistor;
• a third transistor operatively coupled to the data input and the second transistor;
• and
• a fourth transistor operatively coupled to an enablement signal and the third transistor;
• and
• an address output latch operatively coupled to the tri-state input stage, the address output latch including:
• at least one inverter operatively coupled to the second and third transistors of the tri-state input stage;
• and
• a multiplexor operatively coupled in parallel with the at least one inverter, the multiplexor comprising an n-channel transistor and a p-channel transistor in parallel and having their respective gates coupled to complementary control signals and operable for providing a controllable feedback path from an output to an input of the address output latch;
• an address decoder operatively coupled to the at least one inverter of the address output latch;
• an address controller operatively coupled to the address decoder;
• a memory array operatively coupled to the address decoder;
• and
• an input/output circuit operatively coupled to the address decoder, address controller, and memory array.

A dynamic random access memory (DRAM), comprising:

• at least one address buffer, including:
• a multiple state input stage;
• and
• an address output latch operatively coupled to the multiple state input stage, the address output latch comprising:
• at least one inverter;
• and
• a multiplexor operatively coupled in parallel with the at least one inverter, the multiplexor comprising an n-channel transistor and a p-channel transistor in parallel and having their respective gates coupled to complementary control signals and operable for providing a controllable feedback path from an output to an input of the address output latch;
• an address decoder operatively coupled to the at least one inverter;
• an address controller operatively coupled to the address decoder;
• a memory array operatively coupled to the address decoder;
• and
• an input/output circuit operatively coupled to the address decoder, address controller, and memory array.

A dynamic random access memory (DRAM), comprising:

• a plurality of address buffers, each address buffer including:
• a multiple state input stage;
• and
• an address output latch operatively coupled to the multiple state input stage, the address output latch comprising:
• a first inverter;
• at least one second inverter operatively coupled to the first inverter;
• a multiplexor operatively coupled in parallel with both the first and the at least one second inverter, the multiplexor comprising an n-channel transistor and a p-channel transistor in parallel and having their respective gates coupled to complementary control signals and operable for providing a controllable feedback path from an output to an input of the address output latch;
• and
• a third inverter operatively coupled to the at least one second inverter;
• an address decoder operatively coupled to the third inverter of each of the plurality of address buffers;
• an address controller operatively coupled to the address decoder;
• a memory array operatively coupled to the address decoder;
• and
• an input/output circuit operatively coupled to the address decoder, address controller, and memory array.

A dynamic random access memory (DRAM), comprising:

• at least one address buffer, including:
• a multiple state input stage comprising a plurality of transistors operatively coupled in series and at least one of the transistors being operatively coupled to a data input;
• and
• an address output latch operatively coupled to the multiple state input stage, the address latch including:
• at least one inverter;
• and
• a multiplexor coupled in parallel with the at least one inverter;
• an address decoder operatively coupled to the address buffer;
• an address controller operatively coupled to the address decoder;
• a memory array operatively coupled to the address decoder;
• and
• an input/output circuit operatively coupled to the address decoder, address controller, and memory array.

A dynamic random access memory (DRAM), comprising:

• a plurality of address buffers, each of the address buffers including:
• a multiple state input stage comprising a plurality of transistors operatively coupled in series and at least one of the transistors being operatively coupled to a data input;
• and
• an address output latch operatively coupled to the multiple state input stage, the address output latch comprising:
• a first inverter;
• at least one second inverter operatively coupled to the first inverter;
• and
• a multiplexor operatively coupled in parallel with both the first and the at least one second inverter;
• an address decoder operatively coupled to each of the plurality of address buffers;
• an address controller operatively coupled to the address decoder;
• a memory array operatively coupled to the address decoder;
• and
• an input/output circuit operatively coupled to the address decoder, address controller, and memory array.