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US 6,320,816 B2Granted
Column select latch for SDRAM
AssigneeMicron Technology, Inc.
InventorsMirmajid Seyyedy, Jeffrey P. Wright
Life of this patent
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Abstract
A synchronous memory device is described which uses unique column select circuitry. The memory device pipelines address decode and column select operation to increase clock frequency. The column select circuitry includes latches and coupling circuits. The latches are used to latch a column select circuit. The coupling circuit isolates a column select signal from the memory cell columns until an enable signal is provided. The address decode can be combined with an enable signal to reduce the total number of latch circuits needed for a bank of memory cells.
Claims35
A memory device, comprising:
- a memory array having a plurality of memory cells arranged in addressable rows and columns;
- an addressing decode circuit for producing a first decode signal in response to a first portion of an address signal and a second decode signal in response to a second portion of the address signal;
- a first latching circuit for latching the first decode signal to produce a first latched decode signal;
- a second latching circuit for latching the second decode signal to produce a second latched decode signal;
- a first coupling circuit for producing a first column select signal in response to the first latched decode signal and an enable signal;
- a second coupling circuit for producing a second column select signal in response to the second latched decode signal and the first column select signal;
- and
- a column select circuit for activating a column of the memory array in response to the second column select signal.
5 more elements
A memory device, comprising:
- a memory array having a plurality of memory cells arranged in addressable portions;
- an addressing decode circuit for producing a plurality of decode signals in response to an address signal;
- a first latch circuit coupled to the addressing decode circuit for latching a first portion of the plurality of decode signals and producing a first plurality of select signals;
- a second latch circuit coupled to the addressing decode circuit for latching a second portion of the plurality of decode signals and producing a second plurality of select signals;
- a first coupling circuit coupled to the first latch circuit;
- a second coupling circuit coupled to the first coupling circuit and the second latch circuit;
- and
- a select circuit coupled to the second coupling circuit;
- wherein the first coupling circuit is adapted for responding to an enable signal to selectively provide the first plurality of select signals to the second coupling circuit;
- wherein the second coupling circuit is adapted for responding to the first plurality of select signals by selectively providing the second plurality of select signals to the select circuit;
- and
- wherein the select circuit is adapted for responding to the second plurality of select signals by selecting a portion of the memory array.
9 more elements
An address column decode circuit, comprising:
- a first column decode circuit for providing at least one first decode signal in response to an address signal;
- a first latch circuit for providing at least one first latched output;
- at least one first isolation switch interposed between the first column decode circuit and the first latch circuit and adapted for responding to a first control signal by coupling the first column decode circuit to the first latch circuit which latches the at least one first decode signal into the first latch circuit and produces the at least one first latched output;
- a second column decode circuit for providing at least one second decode signal in response to the address signal;
- a second latch circuit for providing at least one second latched output;
- at least one second isolation switch interposed between the second column decode circuit and the second latch circuit and adapted for responding to a second control signal by coupling the second column decode circuit to the second latch circuit which latches the at least one second decode signal into the second latch circuit and produces the at least one second latched output;
- and
- a first coupling circuit coupled to the first latch circuit and adapted for responding to an enable signal by selectively providing the at least one first latched output to a second coupling circuit, wherein the second coupling circuit is coupled to the second latch circuit and is adapted for responding to the at least one first latched output by selectively providing the at least one second latched output to a column select circuit for selecting a column of a memory array in response to the at least one second latched output.
5 more elements
An address column decode circuit, comprising:
- a first column decode circuit for providing at least one first decode signal in response to an address signal;
- a first latch circuit for providing at least one first latched output;
- at least one first isolation switch interposed between the first column decode circuit and the first latch circuit and adapted for responding to a first control signal by coupling the first column decode circuit to the first latch circuit which latches the at least one first decode signal into the first latch circuit and produces the at least one first latched output;
- a second column decode circuit for providing at least one second decode signal in response to an address signal;
- a second latch circuit for providing at least one second latched output;
- at least one second isolation switch interposed between the second column decode circuit and the second latch circuit and adapted for responding to a second control signal by coupling the second column decode circuit to the second latch circuit which latches the at least one second decode signal into the second latch circuit and produces the at least one second latched output;
- and
- a first coupling circuit coupled to the first latch circuit and adapted for responding to an enable signal by selectively providing the at least one first latched output to a second coupling circuit, wherein the second coupling circuit is coupled to the second latch circuit and adapted for responding to the at least one first latched output by selectively providing the at least one second latched output to a column select circuit for selecting a column of a memory array in response to the at least one second latched output;
- wherein the first coupling circuit comprises a logic circuit having the enable signal as a first input and the at least one first latched output as a second input, further wherein the logic circuit has an output for selectively providing the at least one first latched output to the second coupling circuit in response to the enable signal;
- and
- wherein the second coupling circuit comprises a logic circuit having the at least one first latched output as a first input and the at least one second latched output as a second input, further wherein the logic circuit has an output for selectively providing the at least one second latched output to the column select circuit in response to the at least one first latched output.
8 more elements
A memory device, comprising:
- a memory array having a plurality of memory cells arranged in addressable rows and columns;
- an addressing decode circuit for producing a first decode signal in response to a first portion of an address signal and a second decode signal in response to a second portion of the address signal;
- a first latching circuit for latching the first decode signal to produce a first latched decode signal;
- a second latching circuit for latching the second decode signal to produce a second latched decode signal;
- a first logic circuit, having the first latched decode signal and an enable signal as inputs, and a first column select signal as an output;
- a second logic circuit, having the first column select signal and the second latched decode signal as inputs, and a second column select signal as an output;
- and
- a column select circuit for activating a column of the memory array in response to the second column select signal;
- wherein the first and second logic circuits are adapted for selectively electrically isolating the first decode signal and the second decode signal from the column select circuit in response to the enable signal.
6 more elements
A memory device, comprising:
- a memory array having a plurality of memory cells arranged in addressable portions;
- an addressing decode circuit, for producing a plurality of decode signals in response to an address signal;
- a first latch circuit coupled to the addressing decode circuit for latching a first portion of the plurality of decode signals and producing a first plurality of select signals;
- a second latch circuit coupled to the addressing decode circuit for latching a second portion of the plurality of decode signals and producing a second plurality of select signals;
- a first logic circuit coupled to the first latch circuit;
- a second logic circuit coupled to the first logic circuit and the second latch circuit;
- and
- a select circuit coupled to the second logic circuit;
- wherein the first logic circuit is adapted for responding to an enable signal by providing the first plurality of select signals to the second logic circuit when the enable signal is in a first logic state and by electrically isolating the first plurality of select signals from the second logic circuit when the enable signal is in a second logic state;
- wherein the second coupling circuit is adapted for responding to the first plurality of select signals by selectively providing the second plurality of select signals to the select circuit;
- and
- wherein the select circuit is adapted for selecting a portion of the memory array in response to the second plurality of select signals.
9 more elements
A decode circuit, comprising:
- an address decode circuit for coupling to a set of address lines and for providing a first set of decode signals and a second set of decode signals;
- a first latch circuit coupled to the address decode circuit for latching the first set of decode signals;
- a second latch circuit coupled to the address decode circuit for latching the second set of decode signals;
- a first coupling circuit having a first input coupled to the first latch circuit, a second input coupled to an enable line, and an output;
- and
- a second coupling circuit having a first input coupled to the output of the first coupling circuit, a second input coupled to the second latch circuit, and an output for coupling to a select circuit for selecting a memory array portion.
3 more elements
A decode circuit, comprising:
- a first address decode circuit for coupling to a set of address lines;
- a first latch circuit coupled to the first address decode circuit;
- a second address decode circuit for coupling to the set of address lines;
- a second latch circuit coupled to the second address decode circuit;
- a first logic circuit having a first input coupled to the first latch circuit, a second input coupled to an enable line, and an output;
- and
- a second logic circuit having a first input coupled to the output of the first latch circuit, a second input coupled to the second latch circuit, and an output for coupling to a select circuit for selecting a portion of a memory array.
4 more elements
A decode circuit, comprising:
- a first address decoder circuit having a set of input lines for coupling to a set of address lines, and a set of output lines for providing a first set of decode signals;
- a second address decoder circuit having a set of input lines for coupling to the set of address lines, and a set of output lines for providing a second set of decode signals;
- a first set of latches, each having an input coupled to one of the output lines of the first address decoder and an output;
- a second set of latches, each having an input coupled to one of the output lines of the second address decoder and an output;
- a first set of coupling circuits, each having a first input coupled to the output of one of the first set of latches, a second input coupled to an enable line, and an output;
- and
- a second set of coupling circuits, each having a first input coupled to the output of one of the first set of coupling circuits, a second input coupled to one of the outputs of the second set of latches, and an output for coupling to a select circuit for selecting a portion of a memory array.
4 more elements
A memory device, comprising:
- a set of address lines;
- a memory array having selectable portions;
- a select circuit coupled to the memory array;
- and
- a decode circuit coupled to the set of address lines, including:
- an address decode circuit coupled to the set of address lines and for providing a first set of decode signals and a second set of decode signals;
- a first latch circuit coupled to the address decode circuit for latching the first set of decode signals;
- a second latch circuit coupled to the address decode circuit for latching the second set of decode signals;
- a first coupling circuit having a first input coupled to the first latch circuit, a second input coupled to an enable line, and an output;
- and
- a second coupling circuit having a first input coupled to the output of the first coupling circuit, a second input coupled to the second latch circuit, and an output coupled to the select circuit.
8 more elements
A memory device, comprising:
- a set of address lines;
- a memory array having addressable rows and columns of memory cells;
- a column select circuit coupled to the memory array;
- and
- a decode circuit coupled to the set of address lines, including:
- a first address decode circuit coupled to the set of address lines;
- a first latch circuit coupled to the first address decode circuit;
- a second address decode circuit coupled to the set of address lines;
- a second latch circuit coupled to the second address decode circuit;
- a first logic circuit having a first input coupled to the first latch circuit, a second input coupled to an enable line, and an output;
- and
- a second logic circuit having a first input coupled to the output of the first latch circuit, a second input coupled to the second latch circuit, and an output coupled to the column select circuit.
9 more elements
A memory device, comprising:
- a set of address lines;
- a memory array having addressable rows and columns of memory cells;
- a column select circuit coupled to the memory array;
- and
- a decode circuit coupled to the set of address lines, including:
- a first address decoder circuit having a set of input lines coupled to the set of address lines, and a set of output lines;
- a second address decoder circuit having a set of input lines coupled to the set of address lines and having a set of output lines;
- a first set of latches, each having an input coupled to one of the output lines of the first address decoder and an output;
- a second set of latches, each having an input coupled to one of the output lines of the second address decoder and an output;
- a first set of coupling circuits, each having a first input coupled to the output of one of the first set of latches, a second input coupled to an enable line, and an output;
- a second set of coupling circuits, each having a first input coupled to the output of one of the first set of coupling circuits, a second input coupled to one of the outputs of the second set of latches, and an output coupled to the column select circuit.
8 more elements
Dependencies are inferred from the claim text.