Semiconductor device

Abstract

This semiconductor device is equipped with a surplus address detection circuit with a small area and the circuit can be used commonly for various maximum word sizes. The semiconductor comprises a memory for an intermediate word size having X rows or columns, where X is between Nth power of 2 and (N-1)th power of 2, and N is a natural number, an address decoder that decodes address signals addressing rows or columns of the memory for an intermediate word size to be accessed, and a surplus address detection circuit that detects accesses to surplus addresses larger than number X. The address decoder comprises plural pre-decoders that decode address signals classified into plural groups and a post-decoder that generates a selection signal that selects a row or column to be accessed by the combination of outputs of the plural pre-decoders. The surplus address detection circuit detects accesses to surplus addresses larger than number X by the outputs of the plural pre-decoders, and the number of the input signal lines of the surplus address detection circuit is smaller than that of the outputs of the plural pre-decoders, and only a part of the outputs of the plural pre-decoders is supplied to the surplus address detection circuit.

Dependencies are inferred from the claim text.