Decoding of a register file
AssigneeSun Microsystems, Inc.
InventorShree Kant
Life of this patent
Estimating the term…
Abstract
Decoding of addresses in a register file is simplified by reducing the number of bits used for addressing by one. Bits are read from even/odd cell combinations simultaneously, and a reserved address line is driven high. The reserved address line is coupled to each driver corresponding to a storage cell. Individual even cells may also be read. Writing to even/odd cell combinations may be performed in a similar manner. However, when writing, an even write enable line and an odd write enable line are provided to indicate whether an even cell, an odd cell, or an even/odd cell combination should be written to simultaneously. By simplifying the decoding stage, performance of reading and writing tasks may be performed much faster and use less resources.
Claims23
A register file including:
- n storage cells, wherein n is an even number greater than 0, said storage cells divided into even cells and odd cells;
- a predecoding circuit, said predecoding circuit having as input x address bits, where 2x+1=n, and an reserved address line which is always driven high, said predecoding circuit having as output lines indicating a decoded address and said reserved address line;
- and
- n drivers, each of said n drivers being a logical AND gate having an output coupled to one of said storage cells and having as input said lines indicating a decoded address and said reserved address line.
A register file including:
- n storage cells, wherein n is an even number greater than 0, said storage cells divided into even cells and odd cells;
- a predecoding circuit, said predecoding circuit having as input x address bits, where 2x+1=n, an even write enable line, and an odd write enable line, said predecoding circuit having as output lines indicating a decoded address and said two write enable lines;
- and
- n address drivers, each of said n address drivers being a logical AND gate having an output coupled to one of said storage cells and having as input said lines indicating a decoded address;
- and
- wherein each of said n address drivers corresponding to an even cell further has as input said even write enable line and each of said n drivers corresponding to an odd cell further has as input said odd write enable line.
A method for reading information from a register file, said register file having n storage cells, wherein n is an even number greater than 0, said storage cells divided into even cells and odd cells, the method comprising:
- indicating an even cell/odd cell pair to read from by transmitting x address bits to a predecoding circuit, wherein 2x+1=n;
- driving a reserved address high;
- predecoding said address bits;
- transferring said predecoded address to n drivers, each of said drivers corresponding to one of said storage cells;
- transferring said reserved address to said drivers;
- generating a decoded address in two of said drivers, said two of said drivers corresponding to said even cell/odd cell pair;
- and
- sending said decoded address to said even cell/odd cell pair.
A method for reading information from a register file, said register file having n storage cells, wherein n is an even number greater than 0, said storage cells divided into even cells and odd cells, the method comprising:
- indicating an even cell to read from by transmitting x address bits to a predecoding circuit, wherein 2x+1=n;
- driving a reserved address high;
- predecoding said address bits;
- transferring said predecoded address to n drivers, each of said drivers corresponding to one of said storage cells;
- transferring said reserved address to said drivers;
- generating a decoded address in one of said drivers, said one of said drivers corresponding to said even cell;
- and
- sending said decoded address to said even cell pair.
A method for writing information from a register file, said register file having n storage cells, wherein n is an even number greater than 0, said storage cells divided into even cells and odd cells, the method comprising:
- indicating an even cell/odd cell pair to write to by transmitting x address bits to a predecoding circuit, wherein 2x+1=n, driving an even write enable line high, and driving an odd write enable line high, if a write to an even cell/odd cell pair is required, wherein said predecoding circuit is coupled to n drivers, each of said n drivers corresponding to a different cell, said even write enable line coupled to all of said drivers corresponding to even cells and said odd write enable line coupled to all of said drivers corresponding to odd cells;
- indicating an even cell to write to by transmitting x address bits to a predecoding circuit, wherein 2x+1=n, driving an even write enable line high, and driving an odd write enable line low, if a write to an even cell alone is required, wherein said predecoding circuit is coupled to n drivers, each of said n drivers corresponding to a different cell, said even write enable line coupled to all of said drivers corresponding to even cells and said odd write enable line coupled to all of said drivers corresponding to odd cells;
- and
- indicating an odd cell to write to by transmitting x address bits to a predecoding circuit, wherein 2x+1=n, driving an even write enable line low, and driving an odd write enable line high, it a write to odd cell alone is required, wherein said predecoding circuit is coupled to n drivers, each of said n drivers corresponding to a different cell, said even write enable line coupled to all of said drivers corresponding to even cells and said odd write enable line coupled to all of said drivers corresponding to odd cells.
A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform a method for reading information from a register file, said register file having n storage cells, wherein n is an even number greater than 0, said storage cells divided into even cells and odd cells, the method comprising:
- indicating an even cell/odd cell pair to read from by transmitting x address bits to a predecoding circuit, wherein 2x+1=n;
- driving a reserved address high;
- predecoding said address bits;
- transferring said predecoded address to n drivers, each of said drivers corresponding to one of said storage cells;
- transferring said reserved address to said drivers;
- generating a decoded address in two of said drivers, said two of said drivers corresponding to said even cell/odd cell pair;
- and
- sending said decoded address to said even cell/odd cell pair.
A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform a method for reading information from a register file, said register file having n storage cells, wherein n is an even number greater than 0, said storage cells divided into even cells and odd cells, the method comprising:
- indicating an even cell to read from by transmitting x address bits to a predecoding circuit, wherein 2x+1=n;
- driving a reserved address high;
- predecoding said address bits;
- transferring said predecoded address to n drivers, each of said drivers corresponding to one of said storage cells;
- transferring said reserved address to said drivers;
- generating a decoded address in one of said drivers, said one of said drivers corresponding to said even cell;
- and
- sending said decoded address to said even cell pair.
A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform a method for writing information from a register file, said register file having n storage cells, wherein n is an even number greater than 0, said storage cells divided into even cells and odd cells, the method comprising:
- indicating an even cell/odd cell pair to write to by transmitting x address bits to a predecoding circuit, wherein 2x+1=n, driving an even write enable line high, and driving an odd write enable line high, if a write to an even cell/odd cell pair is required, wherein said predecoding circuit is coupled to n drivers, each of said n drivers corresponding to a different cell, said even write enable line coupled to all of said drivers corresponding to even cells and said odd write enable line coupled to all of said drivers corresponding to odd cells;
- indicating an even cell to write to by transmitting x address bits to a predecoding circuit, wherein 2x+1=n, driving an even write enable line high, and driving an odd write enable line low, if a write to an even cell alone is required, wherein said predecoding circuit is coupled to n drivers, each of said n drivers corresponding to a different cell, said even write enable line coupled to all of said drivers corresponding to even cells and said odd write enable line coupled to all of said drivers corresponding to odd cells;
- and
- indicating an odd cell to write to by transmitting x address bits to a predecoding circuit, wherein 2x+1=n, driving an even write enable line low, and driving an odd write enable line high, it a write to odd cell alone is required, wherein said predecoding circuit is coupled to n drivers, each of said n drivers corresponding to a different cell, said even write enable line coupled to all of said drivers corresponding to even cells and said odd write enable line coupled to all of said drivers corresponding to odd cells.
Dependencies are inferred from the claim text.