Multiport memory scheme
AssigneeCypress Semiconductor Corporation
InventorsWarren A. Snyder, Paul D. Berndt
Life of this patent
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Abstract
A circuit comprising a memory array having a first region, a second region, a plurality of bitlines and an X-decoder. A plurality of transistors may each coupled between the first and second regions, where each of the transistors may be configured to (i) separate the first and the second region during a read operation and (ii) join the first and the second region during a write operation. Alternatively, a plurality of memory regions may be implemented, each separated by another plurality of transistors.
Claims18
A circuit comprising:
- a memory comprising (i) a first region, (ii) a second region, (iii) a plurality of bitlines running through said first and second regions and (iv) write decoding circuitry coupled to said first region and said second region;
- and
- a plurality of transistors each coupled in one of said plurality of bitlines between the first and second regions, wherein each of said transistors is configured to (i) electrically separate said first region and said second region during a read operation to enable reading from said first region through a first port and reading from said second region through a second port and (ii) electrically join said first region and said second region during a write operation, wherein said first and second regions are (i) configured to share said write decoding circuitry and (ii) written to only when said regions are joined.
A circuit comprising:
- a memory comprising (i) a first region, (ii) a second region, (iii) a plurality of bitlines running through said first and second regions and (iv) write decoding circuitry coupled to said first region and said second region;
- and
- means for electrically separating said first and said second region to enable reading from said first region through a first port and reading from said second region through a second port and (ii) electrically joining said first region and said second region during a write operation, wherein said first and second regions are (i) configured to share said write decoding circuitry and (ii) written to only when said regions are joined.
A method for dividing a memory comprising the steps of:
- (A) configuring said memory as (i) a first region and (ii) a second region;
- (B) electrically separating said first region and said second region during a read operation and reading said first region from a first port and said second region from a second port;
- (C) electrically joining the first region and the second region during a write operation, wherein said first and second regions are (i) configured to share write decoding circuitry and (ii) written to only when said regions are joined;
- and
- (D) decoding address information for said first region and said second region using said write decoding circuitry.
Dependencies are inferred from the claim text.