Low voltage level power-up detection circuit

A memory device comprising:

• a memory circuit including a memory array and an access circuit for reading data from and writing data into said array;
• and
• a memory circuit power-up detection circuit comprising:
• a transistor for providing a voltage output signal when a first voltage is applied to a supply terminal, said transistor having a gate for receiving a second voltage generated from said first voltage;
• and
• a biasing circuit for applying said second voltage to said gate, said biasing circuit being connected to receive said first voltage from said terminal and including a resistance circuit for dividing said first voltage applied to said terminal to produce said second voltage;
• wherein said resistance circuit is variable for providing different voltage levels for said second voltage.

A processor system comprising:

• a processor;
• and
• a memory device coupled to said processor, said memory device comprising:
• a memory circuit including a memory array and an access circuit for reading data from and writing data into said array;
• and
• a memory circuit power-up detection circuit comprising:
• a transistor for providing a voltage output signal when a first voltage is applied to a supply terminal, said transistor having a gate for receiving a second voltage generated from said first voltage;
• and
• a biasing circuit for applying said second to voltage to said gate, said biasing circuit being connected to receive said first voltage from said terminal and including a resistance circuit for dividing said first voltage applied to said terminal to produce said second voltage;
• wherein said resistance circuit is variable for providing different voltage levels for said second voltage.

A method of detecting a power-up condition of a circuit, said method comprising:

• adjusting a resistance network which is coupled to a voltage supply terminal, which is adapted to receive a first voltage, to produce an adjusted second voltage from an applied said first voltage;
• and
• using said adjusted second voltage to produce a signal indicating a power up condition;
• wherein said adjusting further comprises setting a resistance value in an adjustable resistance network which divides said first voltage.

A method of detecting a power-up condition of a memory device, said memory device having a power-up terminal for receiving a power-up indication signal, said method comprising:

• operating a transistor to produce a voltage output signal when a first voltage is applied to a supply terminal, said transistor receiving second voltage at a gate terminal which is generated from said first voltage;
• receiving said first voltage at a resistance divider circuit and producing said second voltage from said first voltage;
• adjusting the resistance of said resistance divider circuit by setting a resistance value in an programmable resistance network to produce a predetermined value of said second voltage;
• and
• using said voltage output signal to generate a power-up signal at said power-up terminal.