Memory read amplifier circuit with high current level discrimination capacity

A memory read amplifier circuit comprising:

• at least one memory cell to be read and a bit line connected thereto;
• a first pre-charge amplifier circuit connected to said bit line;
• a first circuit connected between a supply voltage and said at least one memory cell for providing a first current to said at least one memory cell, said first circuit comprising at least one transistor including at least one control terminal connected to said first pre-charge amplifier circuit;
• at least one reference memory cell and a reference bit line connected thereto;
• a second pre-charge amplifier circuit connected to said reference bit line;
• a second circuit connected between the supply voltage and said at least one reference memory cell for providing a second current to said at least one reference memory cell, said second circuit comprising at least one transistor including at least one control terminal connected to said second pre-charge amplifier circuit, at least one of said first and second circuits comprising a cascode circuit;
• and
• a differential comparator circuit having a first input connected to the at least one control terminal of said first circuit for receiving a first voltage based upon the first current, and a second input connected to the at least one control terminal of said second circuit for receiving a second voltage based upon the second current, said differential comparator circuit for comparing the first and second voltages for providing a logic value related to a state of said at least one memory cell to be read.

A memory device comprising:

• at least one memory cell and a bit line connected thereto;
• at least one reference memory cell and a reference bit line connected thereto;
• a read amplifier circuit connected to said at least one memory cell and said at least one reference memory cell for reading said at least one memory cell, said read amplifier circuit comprising
• a first pre-charge amplifier circuit connected to said bit line,
• a first cascode circuit connected between a supply voltage and said at least one memory cell for providing a first current to said at least one memory cell, said first cascode circuit comprising at least one transistor including at least one control terminal connected to said first pre-charge amplifier circuit,
• a second pre-charge amplifier circuit connected to said reference bit line,
• a second cascode circuit connected between the supply voltage and said at least one reference memory cell for providing a second current to said at least one reference memory cell, said second cascode circuit comprising at least one transistor including at least one control terminal connected to said second pre-charge amplifier circuit, and
• a differential comparator circuit having a first input connected to the at least one control terminal of said first cascode circuit for receiving a first voltage based upon the first current, and a second input connected to the at least one control terminal of said second cascode circuit for receiving a second voltage based upon the second current, said differential comparator circuit for comparing the first and second voltages for providing a logic value related to a state of said at least one memory cell to be read.

A method for reading a memory device comprising at least one memory cell to be read and a bit line connected thereto, a first pre-charge amplifier circuit connected to the bit line, at least one reference memory cell and a reference bit line connected thereto, and a second pre-charge amplifier circuit connected to the reference bit line, the method comprising:

• providing a first current to the at least one memory cell using a first cascode circuit connected between a supply voltage and the at least one memory cell, the first cascode circuit comprising at least one transistor including at least one control terminal connected to the first pre-charge amplifier circuit;
• providing a second current to the at least one reference memory cell using a second cascode circuit connected between the supply voltage and the at least one reference memory cell, the second cascode circuit comprising at least one transistor including at least one control terminal connected to the second pre-charge amplifier circuit;
• converting the first current to a first voltage and providing the first voltage to a first input of a differential comparator circuit connected to the at least one control terminal of the first cascode circuit;
• converting the second current to a second voltage and providing the second voltage to a second input of the differential comparator circuit connected to the at least one control terminal of the second cascode circuit;
• and
• comparing the first and second voltages for providing a logic value related to a state of the at least one memory cell to be read.