Input/output line precharge circuit and semiconductor memory device adopting the same

A semiconductor memory device comprising:

• first and second data input/output lines;
• a memory cell array including a plurality of memory cells each storing data and accessed by word lines and paired bit lines;
• a row decoder that receives a row address and decodes the received row address to activate one of the word lines;
• a column decoder that receives a column address and decodes the received column address to activate one of column selection lines, thereby connecting one of the paired bit lines to the first and second data input/output lines;
• an input buffer that receives data to be written and generates paired data signals having complementary logic levels during a write operation;
• an input driver that receives the paired data signals to vary the voltages of the first and second data input/output lines according to the paired data signals;
• a sense amplifier that senses the voltages of the first and second data input/output lines and amplifies the voltages during a read operation;
• an output buffer that buffers the outputs of the sense amplifier to output read data;
• and
• a precharge circuit that precharges the first and second data input/output lines for the write and read operations,
• wherein the precharge circuit comprises:
• a first precharge sub-circuit that precharges the first and second data input/output lines to a first level for the write operation;
• and
• a second precharge sub-circuit that precharges at least one of the first and second data input/output lines to a second level for the read operation, the second precharge sub-circuit selectively connecting a first power supply voltage to the first input/output line in response to a first control signal.