Method and apparatus for improving the testing, yield and performance of very large scale integrated circuits

Apparatus for testing devices comprising:

• a device having a plurality of arrays or banks;
• means for applying to the device address and command signals;
• circuit means coupled to the arrays for selectively activating the arrays with respective test mode select signals and test mode control signals;
• test means for applying through the circuit means a sequence of test mode select signals and test mode control signals respectively to each array separately and to all of them simultaneously to reveal whether there are defects or undesirable interactions between or amongst arrays;
• and
• input-output means for sending data to and from the device.

A very large scale integrated (VLSI) device having a plurality of memory arrays and comprising:

• a plurality of spaced-apart arrays on a semiconductor chip;
• command and control means for applying command and control signals to the arrays of the device;
• circuit means coupled to the arrays for selectively activating the arrays with respective test mode signals including test mode select and test mode control signals;
• test means for applying through the circuit means a sequence of the test mode signals respectively to a selected array or arrays to reveal whether there are defects or undesirable interactions between or amongst arrays;
• and
• input-output means for sending data to and from the arrays.

A synchronous dynamic random access memory (SDRAM) device comprising:

• memory arrays placed respectively at quadrants of a semiconductor chip;
• means to apply command and control signals to the device;
• clock means for applying clock signals to the device to synchronize its operation with external equipment;
• logic circuit means coupled to the arrays for selectively activating them in desired test mode sequences with respective test mode control (TMCNTL) signals;
• means for applying TMCNTL signals to the logic circuit means;
• test means for applying to the logic circuit means test mode select (TMSEL) signals such that any combination of the arrays can be activated into any desired test mode sequences by the test mode control (TMCNTL) signals and the TMSEL signals to reveal whether there are defects in the device or undesirable interactions between arrays;
• and
• input-output means for sending data to and from the arrays.

A method of testing devices comprising the steps of:

• providing a device with switching circuitry;
• selecting respective arrays or banks of the device and testing them selectively with separate sequences of test mode control signals to identify interactions and unwanted limitations in the overall performance of the device;
• using the information thus obtained to develop test mode control signals and where indicated to improve the design of the device itself;
• and
• iterating the previous steps to optimize test methodology and the device itself.

A method of testing a synchronous dynamic random access memory (SDRAM) having a plurality of memory arrays located at spaced locations on a semiconductor chip, the method comprising the steps of:

• applying to the memory a series of test mode control (TMCNTL) signals;
• applying test mode select (TMSEL) signals to the memory to selectively apply the TMCNTL signals to the respective memory arrays in a programmed sequence;
• determining from output signals obtained from the respective memory arrays whether there are defects, undesirable interactions and unwanted limitations in the performance of the device;
• and
• iterating the previous steps to optimize a test methodology and the device itself.

A method of testing a device having a plurality of separate sections located at respective locations on a semiconductor chip, the method comprising the steps of:

• choosing a sequence of test modes and their corresponding test mode control (TMCNTL) signals deemed likely to best determine whether there are defects, undesirable interactions amongst the sections, and unwanted limitations in the performance of the device;
• applying the TMCNTL signals to the device;
• simultaneously applying a programmed sequence of test mode select (TMSEL) signals to the device to selectively activate respective sections thereof by the TMCNTL signals in desired sequences and combinations;
• determining from output signals obtained from the respective sections of the device which of the various test modes are best suited in evaluating the device;
• and
• repeating the previous steps in testing other substantially identical devices to optimize a test methodology and the devices themselves.