Redundancy circuit and redundancy method for semiconductor memory device

A semiconductor memory device comprising:

• a plurality of banks, each of the banks comprising a plurality of memory cell array blocks, each of the memory cell array blocks comprising a plurality of sub-blocks, wherein the blocks respectively connect to a plurality of data I/O line pairs, one or more of the data I/O line pairs being redundant, and column select line pairs which control which sub-block in a block is currently connected to the data I/O line pair connected to the block;
• a mode setting circuit that generates a mode signal, the mode signal having states corresponding to a plurality of redundancy modes;
• an input selecting circuit that generates a selecting signal in response to the mode signal and a plurality of signals identifying an area being accessed in the semiconductor memory device;
• and
• a decoding circuit that, in response to the selecting signal, generates a control signal that initiates replacement of a data I/O line pair associated to a defective memory cell in the semiconductor memory device.

A redundancy method for a semiconductor memory device comprising:

• generating a redundancy mode signal, the redundancy mode signal identifying which of a plurality of redundancy modes the memory device is employing;
• selecting from among a plurality of signals identifying a memory area being accessed a selecting signal corresponding to the redundancy mode signal;
• and
• generating a control signal that initiates a replacement of a data I/O line pair associated to a defective block in the memory device, in response to the selecting signal.