Semiconductor memory and nonvolatile semiconductor memory having redundant circuitry for replacing defective memory cell

A nonvolatile semiconductor memory comprising:

• a memory cell array having electrically rewritable memory cells, said memory cell array being divided into a plurality of banks so that while a data write or erase operation is carried out in one of the banks, a data read operation can be carried out in one of the others of the banks;
• at least one redundant column cell array provided in each of said banks for relieving a defective memory cell of said memory cell array;
• a decoding circuit provided in each of said banks;
• a first address bus line for data reading, which is provided commonly for each of said banks;
• a second address bus line for data writing or erasing, which is provided commonly for each of said banks;
• a first data bus line for data reading, which is provided commonly for each of said banks;
• a second data bus line for data writing or erasing, which is provided commonly for each of said banks;
• a plurality of first sense amplifier circuits, connected to said first data bus line, for detecting and amplifying read data of said memory cell array in parallel;
• a plurality of second sense amplifier circuits, connected to said second data bus line, for detecting and amplifying verify read data of said memory cell array in parallel;
• a busy signal circuit, provided in each of said banks, for outputting a busy signal indicating whether an assigned bank is selected as the data write or erase operation or the read operation, said busy signal being used for controlling the selective connection of said first and second address bus lines and for controlling the selective connection of said first and second data bus lines;
• a defective address storing circuit for storing a defective address of said memory cell array and an input/output terminal, to and from which data corresponding to said defective address are inputted and outputted;
• a first redundant sense amplifier circuit which is provided so as to correspond to said redundant column cell array and which is connected to said first data bus line for detecting and amplifying read data of said redundant column cell array;
• a second redundant sense amplifier circuit which is provided so as to correspond to said redundant column cell array and which is connected to said second data bus line for detecting and amplifying verify read data of said redundant column cell array;
• a first address comparator circuit for detecting the coincidence of an address, which is supplied to said first address bus line in the data read operation, with said defective address held in said defective address storing circuit;
• a second address comparator circuit for detecting the coincidence of an address, which is supplied to said second address bus line in the data write or erase operation, with said defective address held in said defective address storing circuit;
• a first switching circuit for replacing a part of the output of said plurality of first sense amplifier circuits with the output of said first redundant sense amplifier circuit, on the basis of a coincidence detection output of said first address comparator circuit;
• and
• a second switching circuit for replacing a part of the output of said plurality of second sense amplifier circuits with the output of said second redundant sense amplifier circuit, on the basis of a coincidence detection output of said second address comparator circuit.

A nonvolatile semiconductor memory comprising:

• a memory cell array having electrically rewritable memory cells, said memory cell array being divided into a plurality of banks so that while a data write or erase operation is carried out in one of the banks, a data read operation can be carried out in one of the others of the banks;
• a redundant cell array block provided in each of said banks for relieving a defective memory cell of said memory cell array;
• decoding circuits provided in said memory cell array and said redundant cell array block in each of said banks respectively;
• a first address bus line for data reading, which is provided commonly for each of said banks;
• a second address bus line for data writing or erasing, which is provided commonly for each of said banks;
• a busy signal circuit, provided in each of said banks, for outputting a busy signal indicating whether an assigned bank is selected as the data write or erase operation or the read operation;
• an address line switching circuit for connecting one of said first and second address bus lines to said memory array and redundant cell array block of each of said banks, in accordance with said busy signal;
• a defective block address storing circuit for storing a defective block address of said memory cell array;
• a first address comparator circuit for comparing an address, which is supplied to said first address bus line, with said defective block address, which has been held in said defective address storing circuit, in the data read operation to output a first coincidence detection signal when both are coincident with each other;
• a second address comparator circuit for comparing an address, which is supplied to said second address bus line, with said defective block address, which has been held in said defective address storing circuit, in the data write or erase operation to output a second coincidence detection signal when both are coincident with each other;
• and
• a hit address switching circuit for causing one of said memory cell array and said redundant cell array block to be active and the other to be inactive, in accordance with said first and second coincident detection signals, in each of said banks.

A nonvolatile semiconductor memory comprising:

• a memory cell array having electrically rewritable memory cells, said memory cell array being divided into a plurality of banks so that while a data write or erase operation is carried out in one of the banks, a data read operation can be carried out in one of the others of the banks, each of said banks having a plurality of cores, each of said cores comprising a set of blocks, each of which is the minimum unit for the data erase operation;
• a redundant cell array block, which has one or more cores provided independently of each of said banks, for relieving a defective memory cell of said memory cell array;
• a first decoding circuit provided in said memory cell array in each of said banks;
• a second decoding circuit provided in said redundant cell array block;
• a first address bus line for data reading, which is provided commonly for each of said banks;
• a second address bus line for data writing or erasing, which is provided commonly for each of said banks;
• a busy signal circuit, provided in each of said banks, for outputting a busy signal indicating whether an assigned bank is selected as the data write or erase operation or the read operation;
• a first address line switching circuit, provided in each of said banks, for connecting one of said first and second address bus lines to said memory array of each of said banks, in accordance with said busy signal;
• a second address line switching circuit, provided in said redundant cell array block, for connecting said first and second address bus lines to said redundant cell array block;
• a defective address storing circuit for storing a defective block address of said memory cell array;
• a first address comparator circuit for comparing an address, which is supplied to said first address bus line, with said defective block address, which has been held in said defective address storing circuit, in the data read operation to output a first coincidence detection signal when both are coincidence with each other;
• a second address comparator circuit for comparing an address, which is supplied to said second address bus line, with said defective block address, which has been held in said defective address storing circuit, in the data write or erase operation to output a second coincidence detection signal when both are coincidence with each other;
• a first core decoder, which is provided in each of said banks and which is activated when said first and second address comparator circuits do not output said first or second coincidence detection signal, for decoding a core address of addresses, which are supplied to said first and second address bus line, to supply the decoded core address to said memory cell array;
• a core switching circuit for selecting an output of said first core decoder in accordance with said busy signal outputted from said busy signal circuit, to supply the selected output to said memory cell array;
• and
• a second core decoder, which is provided in said redundant cell array block and which is activated when said first or second address comparator circuit outputs said first or second coincidence detection signal, for decoding a core address of addresses, which are supplied to said first or second address bus lines, to supply the decoded core address to said redundant cell array block.

A semiconductor memory comprising:

• a memory cell array having electrically rewritable memory cells, said memory cell array also comprising a plurality of blocks, each of which defines a range of memory cells serving as the minimum unit for data erase;
• a redundant cell array for relieving a defective memory cell of said memory cell array;
• a decoding circuit for selecting a memory cell of said memory cell array;
• a defective address storing circuit for storing a defective address of said memory cell array;
• and
• an address comparator circuit for detecting the coincidence of an input address with said defective address which has been held in said defective address storing circuit,
• wherein a defective row of said memory cell array is replaced with said redundant cell array, and
• said decoding circuit has a row decoder for supplying 0 V to a defective word line, which is a word line corresponding to said defective address, of a block to be erased in a data erase operation, a negative voltage to other word lines, and 0 V to all of word lines in blocks other than said block to be erased, to allow said defective word line to be replaced every block of said memory cell array.

A semiconductor memory comprising:

• a memory cell array;
• a redundant cell array for relieving a defective cell of said memory cell array;
• a defective address storing circuit for storing a defective address of said memory cell array;
• and
• an address comparator circuit for detecting the coincidence of an input address with said defective address, which has been held in said defective address storage circuit, to replace said defective cell of said memory cell array with said redundant cell array, and
• wherein said defective address storing circuit comprises:
• an electrically storage circuit for electrically holding a defective address found in a certain defect inspecting process;
• and
• a fixed storage circuit for fixedly storing at least part of said defective address which is transferred to said fixed storage circuit after a plurality of defect inspecting processes.