Semiconductor memory with a decoder circuit having a redundancy relief function
AssigneeOki Electric Industry Co., Ltd.
InventorsHirokazu Miyazaki, Katsuaki Matsui
Life of this patent
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Abstract
The present invention provides a semiconductor memory capable of achieving redundancy relief for column line failure in a stable manner while realizing greater capacity and higher integration. A column decoder circuit CD11 provided in the semiconductor memory is provided with fuse blocks FB(0)˜FB(127), first decoders DA(0)˜DA(127), redundancy control circuits RL(0)˜RL(127) and RLr, second decoders DB(0)˜DB(255), DBr(0) and DBr(1) and column line drivers DV11(0)˜DV11(255), DV11r(0) and DV11r(1). A redundancy control circuit RL(k) is connected with a column line driver DV11(2k) that drives a column line CL(2k) and a column line driver DV11(2k+1) that drives a column line CL(2k+1) via second decoders DB(2k) and DB2(2k+1) respectively.
Claims16
A semiconductor memory provided with a column line decoder circuit comprising:
- n decoders (n is an integer equal to or larger than 1) that each output a SELECTED signal;
- n fuse blocks, each provided with a fuse that is disconnected in correspondence to a column line state;
- and
- a redundancy control circuit group constituted of n+m (m is an integer equal to or larger than 1) redundancy control circuits, wherein a (k+m)th redundancy control circuit (k is an integer equal to or larger than 1 and equal to or smaller than n) selects either the SELECTED signal output by a kth decoder or the SELECTED signal output by a (k+m)th decoder for a respective column line of the semiconductor memory, by employing the n fuse blocks,
- the n fuse blocks being implemented as fuse blocks in an even-numbered column group and fuse blocks in an odd-numbered column group, wherein respective pairs of an even-numbered column group fuse block and an odd-numbered column group fuse block are implemented in two stages along a column line direction.
A semiconductor memory provided with a column line decoder circuit comprising:
- n decoders (n is an integer equal to a larger than 1) that each output a SELECTED signal;
- n fuse blocks, each provided with a fuse that is disconnected in correspondence to a column line state;
- and
- a redundancy control circuit group constituted of n+m (m is an integer equal to or larger than 1) redundancy control circuits, with a (k+m)th redundancy control circuit (k is an integer equal to or larger than 1 and equal to or smaller than n) selecting either said SELECTED signal output by a kth decoder among said n decoders or said SELECTED signal output by a (k+m)th decoder by employing said n fuse blocks, to provide said SELECTED signals thus selected to n+m column lines of the semiconductor memory,
- said n fuse blocks being implemented as fuse blocks in an even-numbered column group and fuse blocks in an odd-numbered column group, wherein respective pairs of an even-numbered column group fuse block and an odd-numbered column group fuse block are implemented in two stages along a column line direction.
A semiconductor memory provided with a column line decoder circuit comprising:
- n first decoders (n is an integer equal to or larger than 1) that each output a SELECTED signal;
- n fuse blocks, each provided with a fuse that is disconnected in correspondence to a column line state;
- a redundancy control circuit group constituted of n+m (m is an integer equal to or larger than 1) redundancy control circuits, with a (k+m)th redundancy control circuit (k is an integer equal to or larger than 1 and equal to or smaller than n) selecting either said SELECTED signal output by a kth first decoder or said SELECTED signal output by a (k+m)th first decoder among said n first decoders by employing said n fuse blocks;
- and
- n+m second decoder units that provide said SELECTED signals selected by individual redundancy control circuits to n+m column line groups of the semiconductor memory each constituted of two or more column lines,
- said n fuse blocks being implemented as fuse blocks in an even-numbered column group and fuse blocks in an odd-numbered column group, wherein respective pairs of an even-numbered column group fuse block and an odd-numbered column group fuse block are implemented in two stages along a column line direction.
Dependencies are inferred from the claim text.