Pseudo-static leakage-tolerant register file bit-cell circuit

A digital processing device comprising:

• a register file to temporarily store digital data within said digital processing device, said register file including:
• a bit line;
• and
• a register file cell including:
• a storage cell to store a digital data bit;
• a first transistor coupled to said bit line;
• and
• a logic circuit to drive an input terminal of said first transistor, said logic circuit to apply a control indication to said input terminal of said first transistor during a read operation when said storage cell includes a digital data bit having a first value, said first transistor to couple said bit line to a ground node in response to said control indication;
• and
• a control unit coupled to said register file, said control unit to deliver instructions to said register file during operation of said digital processing device instructing said register file to perform data storage and retrieval functions.

A register file comprising:

• a bit line;
• and
• a register file cell including:
• a storage cell to store a digital data bit;
• a first transistor connected to said bit line, said first transistor to couple said bit line to a ground node when said first transistor is turned on;
• and
• a logic circuit to drive an input terminal of said first transistor, said logic circuit having a first input to receive a read signal indicative of a current read status of said register file cell and a second input to receive a value related to the digital data bit stored within said storage cell, said logic circuit to turn on said first transistor during a read operation when said digital data bit stored within said storage cell has a first value.

A register file comprising:

• a bit line;
• and
• a register file cell including:
• a storage cell to store a digital data bit;
• a first transistor connected to said bit line;
• a logic circuit to drive an input terminal of said first transistor, said logic circuit to turn on said first transistor when said digital data bit stored in said storage cell has a first value during a read operation;
• and
• a bias circuit coupled to said first transistor to apply a bias voltage to said first transistor when a read operation is not being performed to reduce current leakage through said first transistor from said bit line.