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AssigneeSGS-Thomson Microelectronics S.A.
InventorsFabio Tassan Caser, Mauro Sali, Marcello Cane
Estimating the term…
The invention relates to a row decoding circuit for an electrically programmable and erasable semiconductor non-volatile storage device of the type which includes a matrix of memory cells laid out as cell rows and columns and is divided into sectors, said circuit being input row decode signals and supply voltages in order to drive an output stage incorporating a complementary pair of high-voltage MOS transistors of the pull-up and pull-down type, respectively, which are connected to form an output terminal connected to the rows of one sector of the matrix, characterized in that a MOS transistor of the P-channel depletion type with enhanced gate oxide is provided between the output terminal and the pull-down transistor. The control terminal of the depletion transistor forms a further input of the circuit.
A row decoding method for an electrically programmable and erasable semiconductor non-volatile memory of a type which includes a matrix of memory cells laid out as cell rows and columns and divided into sectors, the memory receiving as inputs row decode signals and supply voltages to drive an output stage that includes an output terminal connected to rows of one sector of the matrix, the method comprising:
A system for selectively performing operations on rows of an electrically programmable and erasable semiconductor non-volatile memory of a type which includes a matrix of memory cells arranged in rows and columns and divided into sectors, each sector including a plurality of the rows of the matrix, the system comprising:
A method of selectively performing operations on rows of an electrically programmable and erasable semiconductor non-volatile memory of a type which includes a matrix of memory cells arranged in rows and columns and divided into sectors, each sector including a plurality of the rows of the matrix, and the matrix connected to a plurality of row decoders to select the sectors of the matrix, each row decoder connected to a respective one of the sectors of the matrix, and each row decoder operative to provide an output signal to each of the plurality of rows of the respective sector, the method comprising:
A system for selectively performing operations on rows of an electrically programmable and erasable semiconductor non-volatile memory of a type which includes a matrix of memory cells arranged in rows and columns and divided into sectors, each sector including a plurality of the rows of the matrix, the system comprising:
Dependencies are inferred from the claim text.