Apparatus for minimization of data line coupling in a semiconductor memory device

Abstract

The present disclosure includes a twist architecture useful for the data lines in a memory device. The architecture involves the twisting of four data lines to create four portions such that each data line occupies a different position in each of the four portions. Specifically, in the first portion, the first data line is adjacent to the second data line, the second data line is adjacent to the third data line, and the third data line is adjacent to the fourth data line; in the second portion, the third data line is adjacent to the first data line, the first data line is adjacent to the fourth data line, and the fourth data line is adjacent to the second data line; in the third portion, the fourth data line is adjacent to the third data line, the third data line is adjacent to the second data line, and the second data line is adjacent to the first data line; and in the fourth portion, the second data line is adjacent to the fourth data line, the fourth data line is adjacent to the first data line, and the first data line is adjacent to the third data line. Such an architecture reduces unwanted parasitic capacitive coupling between the data lines and hence improves speed.

Dependencies are inferred from the claim text.