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US 6,320,779 B1Granted
Die architecture accommodating high-speed semiconductor devices
AssigneeMicron Technology, Inc.
InventorsDonald M. Morgan, Todd A. Merritt
Life of this patent
Estimating the term…
Abstract
In a semiconductor memory device, a die architecture is provided that arranges memory arrays into a long, narrow configuration. Bond pads may then be placed along a long side of a correspondingly shaped die. As a result, this architecture is compatible with short lead frame “fingers” for use with wide data busses as part of high speed, multiple band memory integrated circuits.
Claims6
A method of arranging at least one memory bank on a die that also includes contact pads, comprising:
- dividing a first memory bank into at least two portions;
- and
- positioning each portion of said first memory bank in an area of said die that is distal from other portions of said first memory bank, wherein said area is to at most one side of all contact pads of said die.
Dependencies are inferred from the claim text.