Semiconductor memory with built-in cache
AssigneeOki Electric Industry Co., Ltd.
InventorsYasuhiro Tanaka, Tetsuya Tanabe, Satoru Tanoi
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Abstract
A semiconductor memory device has memory cells for storing data, sense amplifiers for amplifying the stored data, and cache cells in which the amplified data can be placed for quick recall. The cache cells can continue to hold data during memory-cell refresh cycles, permitting the cached data to be accessed quickly afterward. The cache cells may be coupled to column data lines that can be disconnected from the sense amplifiers, enabling memory cells to be refreshed while cache access is in progress. Write buffers may be provided so that when cache data are replaced, the old cache data can be copied back to the memory cells while the new cache data are being accessed.
Claims4
In a semiconductor memory device having word lines, bit lines, memory cells coupled to said word lines and bit lines, sense lines, sense amplifiers coupled to said sense lines, write buffers coupled to said sense lines, column data lines coupled to said sense lines, cache cells coupled to said column data lines, and a data bus, a method of executing a cache hit cycle, comprising the steps of:
- receiving a row address corresponding to data stored in said cache cells;
- transferring data from said cache cells via said column data lines to said sense lines;
- amplifying the data on said sense lines and said column data lines;
- and
- receiving at least one column address and transferring data between said column data lines and said data bus, thereby completing said cache hit cycle.
Dependencies are inferred from the claim text.