Dynamic content addressable memory cell

A method of writing bit data into a dynamic content addressable memory cell for storing and accessing ternary data, comprising the steps of:

• a) holding at a low logic level second and first search lines, the search lines for carrying second and first search bits for comparison respectively with first and second data bits stored in first and second storage devices in the memory cell;
• b) placing bit data on first and second bit lines connected to the first and second storage devices, respectively, for independently writing the first and second data bits to the first and second storage devices, the bit lines distinct from the search lines;
• c) raising to a high logic level a word line, the word line activating first and second access means for coupling the first and second storage devices to the first and second bit lines when raised to a high logic level and deactivating the first and second access means when lowered to a low logic level;
• and
• d) lowering the word line to a low logic level, thereby storing said bit data in the first and second storage devices.

A method of comparing search data with stored data in a dynamic content addressable memory cell for storing and accessing ternary data, comprising the steps of:

• a) precharging to a predetermined precharge voltage level a match line coupled to the dynamic content addressable memory cell;
• b) placing search data on second and first search lines, the search lines for carrying search data for comparing with first and second data bits stored in first and second storage devices in the memory cell, the search lines being distinct from bit lines for reading from and writing to the storage devices;
• and
• c) detecting a voltage change on the match line as an indication of an outcome of comparison between the search data and the stored data.

A method of reading stored data from a dynamic content addressable memory cell for storing and accessing ternary data, comprising the steps of:

• a) holding at a low logic level second and first search lines, the search lines for carrying second and first search bits for comparison respectively with first and second data bits stored in first and second storage devices in the memory cell;
• b) permitting first and second bit lines connected to the first and second storage devices to float at an intermediate voltage, the bit lines distinct from the search lines;
• c) raising to a high logic level a word line, the word line activating first and second access means for coupling the first and second storage devices to the first and second bit lines when raised to a high logic level and deactivating the first and second access means when lowered to a low logic level;
• d) sensing and amplifying a difference of voltage level at each of the first and second bit lines from said intermediate voltage level to indicate read data;
• and
• e) restoring read data into the first and second storage devices.