Electrostatic discharge protection clamp for high-voltage power supply or I/O with nominal-or high-voltage reference

An electrostatic discharge protection circuit for a protected, I/O pad of a semiconductor device to protect its internal circuits from electrostatic discharge, the protected I/O pad being designed to receive voltages during the operation of the internal circuits that are greater than a rated voltage of the semiconductor device, the protection circuit comprising:

• a clamp stage that sinks electrostatic charge from the protected pad to the reference conductor and away from the internal circuits;
• a control stage that activates the clamp stage to couple electrostatic charge from the protected pad and deactivates the clamp stage when the internal circuits are operational by reference to a control signal, which is derived from a reference pad, the control stage comprising an inverter circuit and a clamp driver, the inverter circuit biasing the clamp driver to activate and deactivate the clamp stage;
• and
• a leakage limiting circuit that prevents leakage current through the clamp driver when the protected pad receives a voltage during operation that is at the voltage received by the reference pad by biasing an output node of the clamp driver at a voltage of the reference pad.

An electrostatic discharge protection circuit for a protected, high-voltage pad of a semiconductor device to protect its internal circuits from electrostatic discharge, the protected high-voltage pad being designed to receive voltages during the operation of the internal circuits that are greater than a rated voltage of the semiconductor device, the protection circuit comprising:

• means for sinking electrostatic charge from the protected high-voltage pad to the reference conductor and away from the internal circuits;
• means for activating the sinking means to couple electrostatic charge from the protected high-voltage pad and deactivating the sinking means when the internal circuits are operational by reference to a control signal, which is derived from a reference pad;
• and
• means for preventing leakage current through the activating means when the protected pad receives a voltage during operation that is at the voltage received by the reference pad.

A system board comprising an integrated circuit, which includes an electrostatic discharge protection circuit for a protected, high-voltage pad of a semiconductor device to protect its internal circuits from electrostatic discharge, the protected high-voltage pad being designed to receive voltages during the operation of the internal circuits that are greater than a rated voltage of the semiconductor device, the protection circuit comprising:

• a clamp stage, comprising at least two transistor clamps in a darlington-connected chain between the protected high-voltage pad and a reference conductor, that sinks electrostatic charge from the protected high-voltage pad to the reference conductor and away from the internal circuits;
• a control stage that activates the clamp stage to couple electrostatic charge from the protected high-voltage pad and deactivates the clamp stage when the internal circuits are operational by reference to a control signal, which is derived from a reference pad;
• and
• a leakage limiting circuit that prevents leakage current through the control stage when the protected pad receives a voltage during operation that is at the voltage received by the reference pad.