CMOS active pixel sensor using a pinned photo diode

An active pixel sensor, comprising:

• a substrate having a plurality of pixel areas arranged in rows and columns, and at least one control area such that the control area is associated with at least one pixel.
• a pixel selection circuit having at least one row selection circuit integrated on the substrate capable of selecting one row of pixels, the row selection circuit further comprising a boolean AND (NAND) functioon activated by a binary address indicative of the row in which the pixel resides, the NAND function being coupled to a OR (NOR) function, wherein the row selection circuit further comprises a series of transistors forming the boolean AND (NAND) function implemented using overlaid levels 1 and 2 polysilicon gates;
• a level shifting circuit having coupled to the OR (NOR) function output;
• at least one pixel area comprising:
• a) an optically active area including a printed photodiode, integrated on the substrate in the pixel area, and functioning to accumulate an indication of incoming photons therein;
• and
• b) an optically inactive area, including at least one readout transistor integrated on the substrate in the pixel area and operatively coupled to the pinned photodiode through a transfer gate;
• the readout transistor being formed of a formation process that is compatible with CMOS technology;
• and
• a plurality of correlated double sampling units within the pixel selection circuitry allocated such that there is a correlated double sampling unit for each of the columns.

An active pixel sensor, comprising:

• a substrate having an area, the area functionally divided to form a plurality of pixel areas arranged in rows and columns;
• a pixel selection circuit having at least one row selection circuit integrated on the substrate capable of selecting one row of pixels, the row selection circuit further comprising a boolean AND (NAND) function activated by a binary address indicative of the row in which the pixel resides, the NAND function being coupled to a OR (NOR) function, wherein the row selection circuit further comprises a series of transistors forming the boolean AND (NAND) function implemented using overlaid levels 1 and 2 polysilicon gates;
• a level shifting circuit having coupled to the OR (NOR) function output;
• each of the pixel areas comprising:
• a) a light information receiving element, integrated on the substrate in the pixel area, and functioning to accumulate an indication of incoming light therein;
• and
• b) control electronics, including at least one readout transistor element integrated on the substrate in the pixel area;
• the readout transistor element being formed of a formation process that is compatible with CMOS technology;
• and pixel selection circuitry elements, including a plurality of transistors having controlling gates, wherein at least one of the elements including gates on the substrate overlapping another of the gates on the substrate;
• and
• a correlated double unit allocated for each of the columns outside the pixel area.

An active sensor, comprising:

• substrate;
• at least one pixel area, formed in the substrate, and comprising:
• a) a light information receiving element, integrated on the substrate and functioning to accumulate an indication of incoming photons therein;
• and
• b) a control area, including at least one readout transistor element integrated on the substrate in the pixel area;
• wherein at least a portion of the light information receiving element overlapping and covering at least a portion of the control area;
• the light information receiving element formed of a formation process usually used for CCDs, and the readout transistor element being formed of a foundation process that is compatible with CMOS technology;
• a pixel selection circuit having at least one row selection circuit integrated on the substrate capable of selecting one row of pixels, the row selection circuit further comprising a boolean AND (NAND) function activated by a binary address indicative of the row in which the pixel resides, the NAND function being coupled to a OR (NOR) function, wherein the row selection circuit further comprises a series of transistors forming the boolean AND (NAND) function implemented using overlaid levels 1 and 2 polysilicon gates;
• a level shifting circuit having coupled to the OR (NOR) function output;
• and
• a correlated double sampling unit allocated for each column.

An active sensor, comprising:

• a substrate having an area, the area being functionally divided to form a plurality of pixel areas arranged in rows and columns, and at least one control area;
• each of the pixel areas comprising:
• a) a light information receiving element employing a pinned photodiode integrated on the substrate in the pixel area, and functioning to accumulate an indication of incoming photons therein;
• and
• b) control electronics, including at least one readout transistor element integrated on the substrate in the pixel area, and at least one selection circuit, the selection circuit comprising a plurality of transistors located adjacent one another, and wherein the transistors having gates on the substrate, at least one of the gates on the substrate overlapping another of the gates on the substrate;
• the readout transistor element being formed of a formation process that is compatible with CMOS technology;
• pixel selection circuitry elements, in the control area including a plurality of transistors having controlling gates, wherein at least one of the elements including gates on the substrate overlapping another of the gates on the substrate, and a pixel selection circuit having at least one row selection circuit integrated on the substrate capable of selecting one row of pixels, the row selection circuit further comprising a boolean AND (NAND) function activated by a binary address indicative of the row in which the pixel resides, the NAND function being coupled to a OR (NOR) function, wherein the row selection circuit further comprises a series of transistors forming the boolean AND (NAND) function implemented using overlaid levels 1 and 2 polysilicon gates;
• a level shifting circuit having coupled to the OR (NOR) function output;
• and
• a correlated double sampling unit allocated for each of the columns.

A mixed technology active pixel sensor, comprising:

• a substrate having an area, the area functionally divided to form a plurality of pixel areas arranged in rows and columns, and at least one control area separate from the pixel areas;
• a photodiode element integrated on the substrate in the pixel area, and functioning to accumulate an indication of incoming photons therein;
• at least one readout transistor integrated on the substrate in the pixel area;
• at least one selection transistor, integrated on the substrate in the pixel area to operate in selecting the pixel;
• the readout transistor, and the selection transistor being formed of a formation process that is compatible with CMOS technology;
• a pixel selection circuit having at least one row selection circuit integrated on the substrate capable of selecting one row of pixels, the row selection circuit further comprising a boolean AND (NAND) function activated by a binary address indicative of the row in which the pixel resides, the NAND function being coupled to a OR (NOR) function, wherein the row selection circuit further comprises a series of transistors forming the boolean AND (NAND) function implemented using overlaid levels 1 and 2 polysilicon gates;
• a level shifting circuit having coupled to the OR (NOR) function output;
• and
• a column readout circuit formed in the control area including a double delta sampling circuit formed for each of the columns from a process that is compatible with CMOS technology.

An active pixel sensor that provides correlated double sampling comprising:

• a substrate having an area functionally divided to form a plurality of pixels in a series of columns and rows, and at least one control area outside the area;
• a light information receiving element, integrated on the substrate in the pixel area functioning to accumulate an indication of incoming photons therein, coupled to a transfer gate having clocking means to adjust the voltage of the transfer gate;
• and
• at least one readout transistor element integrated on the substrate in the pixel area, and at least one selection circuit, the selection circuit comprising a plurality of transistors located adjacent one another, a sensing node, a switch, selectively operating to connect the sensing node to the readout transistor element, and a reset switch, operating to connect the sensing node to a reset level;
• a column readout circuit including a double delta sampling circuit formed from a process that is compatible with CMOS technology;
• pixel selection circuitry elements, including a plurality of transistors having controlling gates and a pixel selection circuit having at least one row selection circuit integrated on the substrate capable of selecting one row of pixels, the row selection circuit further comprising a boolean AND (NAND) function activated by a binary address indicative of the row in which the pixel resides, the NAND function being coupled to a OR (NOR) function, wherein the row selection circuit further comprises a series of transistors forming the boolean AND (NAND) function implemented using overlaid levels 1 and 2 polysilicon gates;
• and
• a level shifting circuit having coupled to the OR (NOR) function output.