CMOS image sensor with reduced fixed pattern noise
AssigneeSarnoff Corporation
InventorDonald Jon Sauer
Life of this patent
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Abstract
A correlated double-sampling circuit for sampling an input signal received from a pixel sensor circuit via an input line. According to one embodiment, a first switch selectively couples a junction of first terminals of a first capacitor and a second capacitor to the input line. A second switch selectively couples an output node coupled to a second terminal of the second capacitor to a reference voltage. A third switch selectively couples the output node to an output line.
Claims19
A correlated double-sampling circuit for sampling an input signal received via an input line, the circuit comprising:
- a first switch which selectively couples (a) a junction of first terminals of a first capacitor and a second capacitor to (b) the input line,
- a second switch which selectively couples (c) an output node at a second terminal of the second capacitor to (d) a reference voltage, and
- a third switch which selectively conductively couples the output node to an output line.
A correlated double-sampling circuit for sampling an input signal received via an input line, comprising:
- (a) a capacitor coupled at a first terminal to the input line and coupled at a second terminal to an output node;
- (b) means for applying an initial voltage across the capacitor representative of the difference between an initial input signal and a reference voltage and for applying the reference voltage to the output node during an initial time period;
- (c) means for isolating the output node from the reference voltage during a second time period;
- and
- (d) means for coupling a change in the input signal to the first terminal of the capacitor, wherein the voltage at the output node changes in response to the change in the input signal.
Dependencies are inferred from the claim text.