Circuit and method for generating pixel data elements from analog image data and associated synchronization signals
AssigneeGenesis Microchip Inc.
InventorAlexander J. Eglit
Life of this patent
Estimating the term…
Abstract
A clock recovery circuit in a digital display unit for recovering a time reference signal associated with analog display data. The clock recovery circuit includes a phase-locked loop (PLL) implemented in digital domain and an analog filter to eliminate any undesirable frequencies from the output signal of the PLL. The PLL includes independent control loops to track long term frequency drifts of the time reference signal and the transient phase differences respectively. By providing such independent control loops, the generated clock can be better synchronized with the time reference signal.
Claims11
A circuit for use in a digital display unit of a computer system, and circuit for generating a plurality of pixel data elements from an analog image data received by said digital display unit, said digital display unit further receiving a time reference signal associated with said analog image data, said time reference signal having a high frequency, said circuit comprising:
- an analog-to-digital converter (ADC) for receiving said analog image data, said ADC sampling said analog image data using a sampling clock to generate a plurality of pixel data elements corresponding to said plurality of pixels, wherein said sampling clock has a sampling frequency equal to said high frequency;
- a clock generator circuit comprising a phase-locked loop (PLL) circuit for generating said sampling clock, wherein said sampling clock is synchronized with said time reference signal with a jitter of less than a few nano-seconds, said PLL comprising:
- a discrete time oscillator (DTO) for receiving a digital input and generating a signal representative of said sampling clock with a frequency determined by said digital input;
- and
- a digital circuit for receiving said time reference signal and a feedback signal, wherein said feedback signal is generated by dividing said sampling clock, said digital circuit generating said digital input according to the difference of the phases of said time reference signal and said feedback signal, said digital input causing said DTO to generate said signal synchronized with said time reference signal, said digital circuit comprising:
- a frequency correction logic for adjusting the phase of said sampling clock according to the long-term drifts in the frequency of said time reference signal;
- and
- a phase correction logic for adjusting the phase of said sampling clock according to the phase difference in said feedback signal and said time reference signal,
- wherein said frequency correction logic and said phase correction logic are implemented as two separate control loops,
- wherein a panel interface included in said digital display unit can generate display signals for a display screen based on said plurality of pixel data elements.
Dependencies are inferred from the claim text.