Driving circuit for liquid crystal display in dot inversion method

A circuit for driving a liquid crystal display device with a video data, comprising:

• a latch for latching the video data to output video signals through a plurality of output terminals, the plurality of output terminals being divided into a first group and a second group;
• a clock signal generator producing a first clock signal and a second clock signal, the phase of the first clock signal being 180-degrees from that of the second clock signal;
• a plurality of first logical gates each performing an exclusive OR operation with the first clock signal and the video signal from the first group of the output terminals of the latch to output an operated signal;
• and
• a plurality of second logical gates each performing an exclusive OR operation with the second clock signal and the video signal from the second group of the output terminals of the latch to output an operated signal.

A liquid crystal display device, comprising:

• a first substrate including:
• a plurality of data lines separated as odd data lines and even data lines,
• a plurality of scan lines substantially perpendicular to the plurality of data lines,
• a plurality of pixel electrodes each disposed at areas surrounded by the scan lines and data lines, and
• a plurality of thin film transistors each disposed at a respective intersection of the data lines and the scan lines, a gate of each thin film transistor being connected to an adjacent scan line, a source of each thin film transistor being connected to an adjacent data line, and a drain of each thin film transistor being connected to an adjacent pixel electrode;
• a second substrate opposite the first substrate, the second substrate including a plurality of odd common electrodes and even common electrodes disposed substantially in parallel with the plurality of data lines;
• a liquid crystal material interposed between the first substrate and the second substrate;
• a clock signal generator producing a first clock signal and a second clock signal, the phase of the first clock signal being 180-degrees from that of the second clock signal;
• a common voltage generator applying a first common voltage to the odd common electrodes disposed on the second substrate, and applying a second common voltage to the even common electrodes disposed on the second substrate;
• a data driver connected to the plurality of data lines through one side of the first substrate, the data driver including a latch circuit having a plurality of output terminals each connected to a respective one of the data lines through a respective gate, respective gates connected to the odd data lines receiving the first clock signal to output first pixel driving signals having a predetermined polarity to the respective odd data lines, respective gates connected to the even data lines receiving the second clock signal to output second pixel driving signals having a reverse polarity relative to the first pixel driving signals to the respective even data lines;
• and
• a scan driver outputting scan signals to the plurality of scan lines on the first substrate to drive the thin film transistors connected thereto.