Phase lock loop circuit with loop filter having resistance and capacitance adjustment

A phase lock loop circuit comprising:

• a phase difference detection circuit, formed on a semiconductor substrate, that detects a difference between the phase of a reference signal and the phase of an internal signal and outputs a first detection signal or a second detection signal in conformance to whether the phase of said internal signal is retarded or advanced;
• a voltage-controlled oscillator circuit that outputs an oscillation signal having a frequency corresponding to a control voltage applied thereto;
• a feedback circuit that generates said internal signal based upon said oscillation signal and provides said internal signal to said phase difference detection circuit;
• and
• a filter circuit that generates said control voltage and outputs said control voltage through an output node thereof, wherein
• said filter circuit is provided with:
• a first means for switching that implements ON/OFF control of electrical connection between a first source potential and a first node based upon said first detection signal;
• a first transistor located between said output node and said first node, and whose on resistance is controlled by a first bias voltage supplied to a control electrode thereof;
• a second transistor located between a second node and said output node, and whose on resistance is controlled by a second bias voltage supplied to a control electrode thereof;
• a second means for switching that implements ON/OFF control of electrical connection between a second source potential and said second node based upon said second detection signal;
• a means for voltage division that includes a first resistance portion and a second resistance portion, and that divides the voltage between said first source potential and said second source potential at said first resistance portion and said second resistance portion to generate said second bias voltage;
• a means for bias generation, located between said first source potential and said second source potential, that controls a current input thereto with said second bias voltage, and generates said first bias voltage based upon the current input thereto;
• and
• a capacitive means, located between said output node and said second source potential, that prevents fluctuation of said control voltage by holding a voltage corresponding to said control voltage.