Lock detector for phase-locked loop
AssigneeAgere Systems Guardian Corp.
InventorsDonald H. Friedberg, Dale Harvey Nelson, Lai Q. Pham
Life of this patent
Estimating the term…
Abstract
A method and lock detector for detecting lock between a reference signal and a feedback signal of a PLL circuit. A number of clock cycles of the feedback signal is counted during consecutive test intervals defined by the reference signal. A feedback comparator determines whether the number of clock cycles of the feedback signal during a given test interval is within an expected range. Before lock has been indicated, a qualification counter is either incremented or reset after each test interval in accordance with the expected range determination. A lock indication signal indicating that lock has been achieved is provided if said qualification counter exceeds a qualification threshold.
Claims14
A method for detecting lock between a reference signal and a feedback signal, comprising the steps of:
- (a) counting a number of clock cycles of the feedback signal during consecutive test intervals defined by counting a number of clock cycles of the reference signal;
- (b) determining whether the number of clock cycles of the feedback signal during a given test interval is equal to an expected value within a specified degree of tolerance;
- (c) before lock has been indicated, incrementing or resetting a qualification counter after each test interval in accordance with the determination of step (b);
- and
- (d) indicating that lock has been achieved if said qualification counter exceeds a qualification threshold.
An integrated circuit having a lock detector for detecting lock between a reference signal and a feedback signal, the lock detector comprising:
- (a) a feedback counter for counting a number of clock cycles of the feedback signal during consecutive test intervals defined by counting a number of clock cycles of the reference signal;
- (b) a comparator for determining whether the number of clock cycles of the feedback signal during a given test interval is equal to an expected value within a specified degree of tolerance;
- and
- (c) a finite state machine for incrementing or resetting a qualification counter, before lock has been indicated, after each test interval in accordance with the determination of said comparator and for providing a lock indication signal if said qualification counter exceeds a qualification threshold.
Dependencies are inferred from the claim text.