Amplifier circuit

An amplifier circuit comprising:

• (a) a peak amplifier signal path, said peak amplifier signal path comprising:
• a peak amplifier having an input port and an output port;
• and
• means, coupled to said peak amplifier, for optimizing the power added efficiency of said peak amplifier in the backed off state wherein said means does not introduce an impedance transformation;
• and
• (b) a carrier amplifier signal path, said carrier amplifier signal path comprising:
• a carrier amplifier having an input port and output port;
• and
• means, coupled to said carrier amplifier, for equalizing the time delay in said carrier amplifier signal path and said peak amplifier signal path.

A method for providing an amplifier circuit comprising the steps of:

• providing a first amplifying device;
• matching the input impedance of said first amplifier device;
• power matching the output impedance of said first amplifier device;
• providing a second amplifying device;
• power matching the output impedance of said second amplifying device;
• matching the input impedance of said second amplifier device under low signal conditions;
• selecting a delay line coupled to the output port of the second amplifying device such that the second delay line provides a delay chosen to optimize the power added efficiency of the amplifier in the backed off state;
• and
• selecting a delay line provided by a second delay line coupled to the input port of said first amplifying device such that the delay provided by the second delay line equalizes the signal path length from the input of the delay line through the output of the output matching network coupled to the first amplifying device and the input port of the input matching network coupled to the second amplifying device to the output port of the second delay line.

A method for providing an amplifier circuit comprising the steps of:

• providing a first amplifying device;
• matching the input impedance of said first amplifier device;
• power matching the output impedance of said first amplifier device;
• providing a second amplifying device;
• power matching the output impedance of said second amplifying device;
• matching the input impedance of said second amplifier device under low signal conditions;
• selecting a delay line coupled to the output port of the second amplifying device such that the second delay line provides a delay chosen to optimize the power added efficiency of the amplifier in the backed off state;
• and
• selecting a delay line provided by a second delay line coupled to the input port of said first amplifying device such that the delay provided by the second delay line equalizes the signal path length from the input of the delay line through the output of the output matching network coupled to the first amplifying device and the input port of the input matching network coupled to the second amplifying device to the output port of the second delay line;
• wherein the first amplifying device corresponds to a carrier amplifier and the second amplifying device corresponds to a peak amplifier and wherein the delay provided by the peak amplifier delay line is selected such that the signals provided by the carrier amplifier and the peak amplifier can be efficiently combined and to optimize the power added efficiency of the amplifier circuit in the backed off state.

An amplifier circuit having an input port and an output port, the amplifier circuit comprising:

• a carrier amplifier having an input port coupled to the input port of the amplifier circuit and having an output port;
• a peak amplifier having an input port coupled to the input port of the amplifier circuit and having an output port;
• and
• a first delay line having a first port coupled to the output port of said peak amplifier and having a second port coupled to the output port of the amplifier, wherein said first delay line provides a phase shift and said phase shift is a linear function of frequency and said first delay line does not introduce an impedance transformation.