Boost circuit
AssigneeNEC Corporation
InventorNaoaki Sudo
Life of this patent
Estimating the term…
Abstract
Boost circuit units are connected in parallel. A boost output voltage VBOOST′ of a dummy boost circuit unit having the same configuration as the boost circuit units is detected by a voltage detection circuit. The voltage detection circuit outputs a signal TBST2 which becomes “high” when VBOOST′ is lower than VLIMIT and “low” when VBOOST′ is equal to or higher than VLIMIT. The TBST2 signal is input to a NAND circuit. When a “high” signal is input to the NAND circuit, an input voltage ATDBST2 is input to the boost circuit unit as well via the NAND circuit and the two boost circuit units perform boost operation. Thus, a boost circuit can suppress the dispersion of the boost voltage caused by the dispersion of the process condition and the variation of the external temperature besides the variation of the power supply voltage Vcc.
Claims5
A boost circuit comprising:
- a main part of the boost circuit having a plurality of (n) boost circuit units connected in parallel;
- a boost voltage detection section having a dummy boost circuit unit having same configuration as the boost circuit units of the main part of the boost circuit, and a voltage detection circuit for detecting an output voltage of only the dummy boost circuit unit;
- and
- a selection circuit for selecting a number of boost circuit units to be activated in the main part of the boost circuit, based on a result of detection of the boost voltage detection section.
A boost circuit comprising:
- a main part of the boost circuit having a plurality of (n) boost circuit units connected in parallel;
- a boost voltage detection section having a dummy boost circuit unit having same configuration as the boost circuit units of the main part of the boost circuit, and a voltage detection circuit for detecting an output voltage of the dummy boost circuit unit and comparing the output voltage of the dummy boost circuit unit with a specific voltage VLIMIT and outputting a “high” or “low” test signal;
- and
- a selection circuit for selecting a number of boost circuit units to be activated in the main part of the boost circuit, based on a result of detection of the boost voltage detection section,
- wherein the main part of the boost circuit comprises an input terminal for inputting a signal to the boost circuit units connected in parallel, and an output terminal for outputting a signal supplied from the boost circuit units connected in parallel, and
- wherein the selection circuit comprises an inverter connected between the input terminal and a first boost circuit unit, (n−1) NAND circuits respectively connected between the input terminal and second to nth boost circuit units, and a circuit for inputting the test signal to the NAND circuits.
Dependencies are inferred from the claim text.