RC delay time stabilizing circuit
AssigneeHyundai Electronics Industries Co., Ltd.
InventorYoung-Han Jeong
Life of this patent
Estimating the term…
Abstract
A RC delay time stabilizing circuit of the present invention includes an inverter which inverts a periodic input signal, a RC delay unit which is charged/discharged in accordance with an output from the inverter, a pull-up MOS transistor connected between a source voltage terminal and an output terminal of the RC delay unit and having a gate for receiving the input signal, and an output unit which generates an output signal having an identical delay time in accordance with output levels of the inverter and the RC delay unit. Such RC delay time stabilizing circuit of the present invention decreases the charging time of the RC delay unit when a periodic signal is inputted, thus being able to maintain the same delay time in each cycle of the input signal.
Claims14
A RC delay time stabilizing circuit, comprising:
- an inverter inverting a periodic input signal;
- a RC delay unit being charged/discharged in accordance with an output from the inverter;
- a pull-up MOS transistor connected between a source voltage terminal and an output terminal of the RC delay unit and having a gate for receiving the input signal;
- and
- an output unit that generates an output signal which has a substantially uniform delay time relative to the periodic input signal in accordance with output levels of the inverter and the RC delay unit, wherein the output unit comprises,
- first to third MOS transistors serially connected between a first prescribed voltage and a second prescribed voltage, and
- a fourth MOS transistor connected in parallel to drains of the second and third MOS transistors and to an output terminal of the output unit, wherein gates of the first and fourth MOS transistors are connected with the output terminal of the RC delay unit.
A RC delay time stabilizing circuit, comprising:
- an inverter that inverts periodic input signals;
- a RC delay unit coupled to an output terminal on the inverter;
- a pull-up device connected between a first prescribed voltage and an output terminal of the RC delay unit, wherein the pull-up device receives the periodic input signals and pulls up the output terminal of the RC delay unit responsive to a prescribed transition of the periodic input signals;
- and
- an output unit connected to the output terminal of the inverter and an output terminal of the RC delay unit, wherein the output unit generates output signals each having a substantially identical delay time from a corresponding one of the periodic input signals, and wherein the output unit comprises,
- a plurality of transistors connected in series between the first prescribed voltage and a second prescribed voltage, wherein an output terminal of the output unit is connected between two of the plurality of transistors, and
- an additional transistor having a first electrode coupled to the output terminal of the output unit, wherein a control electrode of the additional transistor is connected with the output terminal of the RC delay unit.
A RC delay time stabilizing circuit, comprising:
- a logic gate logically processing periodic input signals;
- a RC delay unit being charged/discharged in accordance with the logically processed periodic input signals from the logic gate;
- and
- an output unit coupled to the logic gate and the RC delay unit that outputs delayed signals at an output terminal, each having a substantially identical delay time relative to a corresponding one of the periodic input signals, wherein the output unit comprises,
- first to third MOS transistors serially connected between a source voltage and a ground voltage;
- and
- a fourth MOS transistor connected in parallel to drains of the second and third MOS transistors and to the output terminal of the output unit, wherein gates of the first and fourth MOS transistors are connected with an output terminal of the RC delay unit.
Dependencies are inferred from the claim text.