Dual clock D type flip-flop

A method of indicating a detection of two signal events, said method comprising:

• providing an active output signal upon a first event of an edge of a first clock signal occurring during an activation of a first data signal;
• deactivating said output signal upon a second event of an edge of a second clock signal occurring during an activation of a second data signal;
• after each first event, preventing said output signal from being affected by said first clock signal and said first data signal until after a subsequent second event has occurred;
• after each second event, preventing said output signal from being affected by said second clock signal and said second data signal until after a subsequent first event has occurred;
• and
• using a multiplexer for locking out any effect of a subsequent activation of said first data signal until after said event on said activation of said first data signal occurs.

A dual clock D type flip-flop, comprising:

• means for outputting an output signal in an active state after an occurrence of a first event on a first data input line triggered by an edge of a first clock signal;
• means for maintaining a state of said output signal in an active state until a second event is detected on a second data input line based on a second clock signal;
• means for deactivating said output signal upon said detection of said second event on said second data input line based on said second clock signal:
• and
• multiplexer means for locking out any effect of a subsequent event on said first data input line until after said event on said first data input line occurs.

Apparatus for indicating a detection of two signal events, comprising:

• means for providing an active output signal upon a first event of an edge of a first clock signal occurring during an activation of a first data signal;
• means for deactivating said output signal upon a second event of an edge of a second clock signal occurring during an activation of a second data signal;
• means for preventing, after each first event, said output signal from being affected by said first clock signal and said first data signal until after a subsequent second event has occurred;
• means for preventing, after each second event, said output signal from being affected by said second clock signal and said second data signal until after a subsequent first event has occurred;
• and
• multiplexer means for locking out any effect of a subsequent event on said first data input line until after said event on said first data input line occurs.

A dual clock flip-flop comprising:

• a first single clock flip-flop adapted to change a state of an output signal thereof based on an occurrence of an event on a first data line input thereto as determined by a clock signal input thereto;
• a second single clock flip-flop adapted to change a state of an output signal thereof based on an occurrence of an event on a second data line input thereto as determined by a clock signal input thereto;
• and
• a first logic circuit to provide an output data signal for said dual clock flip-flop comprising an exclusive OR of said output signal of said first single clock flip-flop and said output signal of said second single clock flip-flop,
• a second logic circuit comprising:
• a first multiplexer circuit providing said first data line input to said first single clock flip-flop;
• and
• a second multiplexer circuit providing said second data line input to said second single clock flip-flop.