Duty-cycle correction driver with dual-filter feedback loop

A duty-cycle corrector comprising:

• a clock input for an input clock;
• a modulator for altering rising and falling-transition slew rates in response to a control signal, the modulator outputting an intermediate clock;
• wherein the modulator comprises:
• a source-limiting p-channel transistor having a gate coupled to the control signal and a source connected to a power supply, for limiting charging current in response to the control signal;
• a switching p-channel transistor, coupled to receive charging current from the source-limiting p-channel transistor, having a gate coupled to the input clock and a drain driving the intermediate clock;
• a source-limiting n-channel transistor having a gate coupled to the control signal and a source connected to a ground supply, for limiting discharging current in response to the control signal;
• and
• a switching n-channel transistor, coupled to sink discharging current to the source-limiting n-channel transistor, having a gate coupled to the input clock and a drain driving the intermediate clock;
• a driver, receiving the intermediate clock and driving an output clock;
• an error amp having a reference input and a sensing input, for generating the control signal in proportion to a difference between the sensing input and the reference input;
• an output capacitor, coupled between the control signal and a ground, for reducing ripple on the control signal;
• a series resistor, coupled between the output clock and the sensing input;
• and
• an input capacitor, coupled between the sensing input and the ground, the series resistor and the input capacitor forming a detector filter while impedance of the error amp and the output capacitor forming a second filter,
• whereby two filters in a feedback loop adjust the control signal to modulate the input clock.

A duty-cycle correction circuit comprising:

• modulator means, receiving an input clock with an unadjusted duty cycle, for adjusting rise and fall slew rates of an intermediate clock generated by the modulator means in response to a control voltage to adjust duty cycle;
• driver means, receiving the intermediate clock, for buffering the intermediate clock to generate a measured clock, the measured clock having an adjusted duty cycle;
• detector means, coupled to receive the measured clock, for integrating the measured clock to generate a filtered clock, the detector means including a series resistor between the measured clock and an input capacitor on a sensing node;
• differential amp means, receiving the sensing node from the detector means, for comparing the sensing node to a reference voltage to generate the control voltage;
• and
• output capacitor means, coupled between the control voltage and a ground, for filtering the control voltage;
• wherein the modulator means comprises:
• source-limiting p-channel transistor means, having a gate coupled to the control voltage, for limiting charging current in response to the control voltage;
• switching p-channel transistor means, coupled to receive charging current from the source-limiting p-channel transistor means, having a gate coupled to the input clock, for driving the intermediate clock with the charging current;
• source-limiting n-channel transistor means, having a gate coupled to the control voltage, for limiting discharging current in response to the control voltage;
• and
• switching n-channel transistor means, coupled to sink discharging current to the source-limiting n-channel transistor means, having a gate coupled to the control voltage, for driving the intermediate clock,
• whereby the source-limiting p-channel and n-channel transistor means limit current to control rising and falling-transition slew rates of the intermediate clock and whereby feedback includes two filters, an input filter having an RC time constant defined by the input capacitor and series resistor, and an output filter having an RC time constant defined by the output capacitor means and an impedance of the differential amp means.