PLL circuit which can reduce phase offset without increase in operation voltage

Abstract

A PLL circuit includes a comparator, an integrator, a phase controller, a current control oscillator and a feedback frequency divider. The comparator compares a phase of an input signal with a phase of a feedback signal to generate a comparison result. The integrator generates a first current to control an oscillation frequency of an output signal based on the comparison result. The phase controller controls a phase of the output signal based on the comparison result such that a phase difference between the phase of the input signal and the phase of the output signal at a lock state is reduced to generate a second current. The current control oscillator generates the output signal. The output signal oscillates at a frequency corresponding to a third current, wherein the first current and the second current add up to the third current. The feedback frequency divider performs a frequency division on the output signal to generate the feedback signal to send to the comparator.

Dependencies are inferred from the claim text.