Circuit and method for generating a synchronous clock signal
AssigneeTexas Instruments Incorporated
InventorsJeff Chang, Y. K. Chu, Lilium Hsu
Life of this patent
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Abstract
A method for generating a synchronous clock signal and a circuit (10) for implementing the method described. To generate the positive-going transition of the clock signal, the method generates a synchronization pulse train using a synchronization signal input. The method generates a second pulse train, having pulses offset in time from and later than those of the synchronization pulse train, to generate the negative-going transition of the clock signal. Because there is little loss in duty cycle, when the synchronous clock signal is input to a power factor correction (“PFC”) and pulse width modulation (“PWM”) controller circuit, the PFC and PWM controller is able to operate normally.
Claims14
A circuit for generating a synchronous clock signal, said circuit having an external synchronization signal as an input, said circuit comprising:
- a synchronization circuit, to which said synchronous clock signal is fed back, that uses said synchronization signal to generate a first train of pulses;
- a ramp and pulse generator, to which said synchronous clock signal is fed back, that generates a second train of pulses offset in time from said first pulse train;
- and
- a clock generator having as inputs said first and second pulse trains and generating said synchronous clock signal.
A circuit for generating a clock signal having synchronous and asynchronous portions, said circuit comprising:
- a synchronization circuit having as inputs a synchronization signal and said clock signal, said synchronization circuit generating a first train of pulses;
- a ramp and pulse generator, having as an input said clock signal, for generating a second train of pulses offset in time from said first pulse train, and generating a third train of pulses earlier in time than that of said second pulse train;
- and
- a clock generator having as inputs said first, second, and third pulse trains,
- wherein each pulse of said first pulse train generates a positive-going transition for said synchronous clock signal portion, each pulse of said third pulse train generates a positive-going transition for said asynchronous clock signal portion, and each pulse of said second pulse train generates a negative-going transition for said synchronous and asynchronous clock signal portions, said clock generator generating said clock signal.
A method for generating a synchronous clock signal, said method comprising the steps of:
- generating a first pulse train using said synchronous clock signal and a synchronization signal with a synchronization circuit, each pulse of said first pulse train generating a positive-going transition for said synchronous clock signal;
- generating a second pulse train using said synchronous clock signal with a ramp circuit, said second pulse train having pulses offset in time from and later than pulses of said first pulse train, each pulse of said second pulse train generating a negative-going transition for said synchronous clock signal;
- and
- generating said synchronous clock signal using said first pulse train and said second pulse train.
A method for generating a clock signal having synchronous and asynchronous portions, said method comprising the steps of:
- generating a first pulse train using said clock signal and a synchronization signal with a synchronization circuit, each pulse of said first pulse train generating a positive-going transition for said synchronous clock signal portion;
- generating a second pulse train using said clock signal with a ramp circuit, each pulse of said second pulse train generating a positive-going transition for said asynchronous clock signal portion;
- generating a third pulse train using said clock signal with said ramp circuit, said third pulse train having pulses offset in time from and later than pulses of said first and second pulse trains, each pulse of said third pulse train generating a negative-going transition for said synchronous and asynchronous clock signal portions;
- generating a ramp signal which is used to generate said third pulse train;
- generating said clock signal using said first, second and third pulse trains;
- and
- wherein a portion of each period of said ramp signal does not have to remain at zero volts until an associated first pulse train pulse ends.
Dependencies are inferred from the claim text.