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US 6,320,432 B1Granted
Output buffer circuit
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorChuma Nagao
Life of this patent
Estimating the term…
Abstract
An output buffer circuit which is formed by transistors 4 to 7 and 15 to 18 and in which the potential of the output signal OUT detected by a capacitance 8 or 19 is fed back to an output transistor 1 or 12 to control its gate potential so that the output signal OUT reaches the high- or low-level in a constant time regardless of a change in the value of a load capacitance connected to the output terminal.
Claims10
An output buffer circuit comprising:
- an output transistor which supplies a voltage to an output signal to be output from an output terminal in accordance with the level of an input signal fed via an input terminal;
- a capacitance for detecting the potential of said output signal;
- feedback control means formed by a transistor and connected between said capacitance and said output transistor, for feeding back the potential of said output signal detected by said capacitance to control the gate potential of said output transistor and control the driving power of said output transistor so that said output signal reaches a predetermined level in a fixed time regardless of a change in the capacitance of a load connected to said output terminal;
- and
- a control transistor for turning OFF said the operation of said feedback control means when said output signal is not output.
2 more elements
Dependencies are inferred from the claim text.