High-speed, low-power continuous-time CMOS current comparator

Abstract

A CMOS current comparator featuring shortened response delay times lower power consumption, smaller area and enhanced process robustness. The current comparator is comprised of a CMOS complementary amplifier, two resistive-load amplifiers and two CMOS inverters. The CMOS complementary amplifier receives an input current from an input node which generates an output voltage at a corresponding output node. The CMOS complementary amplifier is comprised of an N-type metal oxide semiconductor field effect transistor (NMOS) and a P-type metal oxide semiconductor field effect transistor (PMOS) connected in series. Control gates on both the NMOS and PMOS are connected to form the input node. NMOS and PMOS drain electrodes are also coupled to the output node. The CMOS complementary amplifier further has a resistive feedback circuit which is connected between the input and output nodes. The two resistive-load amplifiers are connected in cascade form to receive and amplify output voltage from the CMOS complementary amplifier. The result being a correspondingly output of amplified voltage. The two CMOS inverters are also connected in cascade form to receive the amplified voltage and output corresponding rail-to-rail result signal.

Dependencies are inferred from the claim text.