Method of providing and circuit for providing phase lock loop frequency overshoot control

A clocking system comprising a phase frequency detector device to receive a reference clock signal and a feedback clock signal, said phase frequency detector device to provide a first signal based on the reference clock signal and the feedback signal, a width of said first signal being based on a difference between said reference clock signal and said feedback clock signal, said phase frequency detector device to alter the width of said first signal and to output a second signal, wherein said first signal is applied to a first input of a first circuit component, said first circuit component to output said second signal to a first delay circuit, an output of said first delay circuit being applied to a second input of said first circuit component.

A phase lock loop system comprising a phase frequency detector device to receive a reference clock signal and a feedback clock signal and to provide a first control signal and a second control signal, said phase lock loop system including a width control circuit to alter a width of said first control signal and to produce an altered first control signal, wherein the width control circuit comprises a first delay circuit and a second delay circuit, said first delay circuit comprises a current starved delay circuit coupled to an internal bias of the phase lock loop system, wherein a delay of said first delay circuit determines a width of the altered first control signal and a delay of the second delay circuit determines a width of the altered second control signal.

A phase lock loop system comprising a phase frequency detector device to receive a reference clock signal and a feedback clock signal and to provide a first control signal and a second control signal, said phase lock loop system including a width control circuit to alter a width of said first control signal and to produce an altered first control signal, wherein subsequent to synchronization between the reference clock signal and said feedback clock signal, portions of a phase error are ignored that exceed a delay of said phase lock loop system.

A clocking system comprising a phase frequency detector device to receive a reference clock signal and a feedback clock signal, said phase frequency detector device to provide a first signal based on the reference clock signal and the feedback signal, a width of said first signal being based on a difference between said reference clock signal and said feedback clock signal, said phase frequency detector device to alter the width of said first signal using a delay circuit and to output a second signal, wherein the delay circuit comprises a current starved delay circuit coupled to an internal bias of the clocking system.