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US 6,320,423 B1Granted
MOS logic circuit and semiconductor apparatus including the same
AssigneeSharp Kabushiki Kaisha
InventorYuichi Sato
Life of this patent
Estimating the term…
Abstract
A MOS logic circuit includes: a pass-transistor logic circuit, including at least one first MOS transistor, for performing a predetermined logic operation to provide an output; and an amplifying circuit, including at least one second MOS transistor, for enhancing a driving capability of the output of the pass-transistor logic circuit. Each of the first MOS transistor and the second MOS transistor is a DTMOS transistor having a gate connected to an associated well in which a channel thereof is formed.
Claims7
A MOS logic circuit, comprising:
- a pass-transistor logic circuit for performing a predetermined logic operation to provide an output, said pass-transistor logic circuit including a first DTMOS transistor having a threshold voltage;
- and
- an amplifying circuit for enhancing a driving capability of said output without employing a pull-up PMOS transistor, said amplifying circuit including a second DTMOS transistor having an absolute value of a threshold voltage higher than that of said first DTMOS transistor when said second DTMOS transistor is in an off state and said first DTMOS transistor is in an on state to prevent leakage of a stationary penetrating current through said amplifying circuit, thereby lowering power consumption of the MOS logic circuit,
- wherein each of said DTMOS transistors have a gate connected to an associated well in which a channel thereof is formed, said gate and associated well short-circuited to prevent an increase in threshold voltage due to a back gate effect, thereby reducing the number of pass-transistor and amplifier elements required in the MOS logic circuit.
1 more element
A MOS logic circuit, comprising:
- a first DTMOS transistor for performing a precharge operation to produce a charge;
- a determination circuit for discharging or holding said charge of said first DTMOS transistor to determine a logic based on an input signal, said determination circuit including a second DTMOS transistor;
- and
- an amplifying circuit for amplifying an output from said determination circuit without employing a pull-up PMOS transistor, said amplifying circuit including a third DTMOS transistor,
- wherein each of said DTMOS transistors have a gate connected to an associated well in which a channel thereof is formed, said gate and associated well short-circuited to prevent an increase in threshold voltage due to a back gate effect, thereby reducing the number of pass-transistor and amplifier elements required in the MOS logic circuit;
- and
- wherein the logic circuit does not include any PMOS and NMOS transistors.
4 more elements
Dependencies are inferred from the claim text.