Complementary source coupled logic
AssigneeNational Semiconductor Corporation
InventorYongseon Koh
Life of this patent
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Abstract
A complementary source coupled logic topology suitable for low voltage differential signaling is disclosed. The topology is referred to as complementary source coupled logic as it contains complementary differential paris and complementary source follows. The complementary differential pair provide low voltage swing, low gain, high bandwidth signaling with rail-to-rail input common-mode range. The complementary source followers combine and buffer the outputs of complementary differential pairs preserving the low voltage swing, low gain and high bandwidth.
Claims28
A differential circuit having a high bandwidth over a rail-to-rail common mode range, said differential circuit comprising:
- a first differential pair receiving first and second differential inputs;
- a first pair of active loads coupled between said first differential pair and a first power source;
- a first current source coupled between said first differential pair and a second power source;
- a second differential pair receiving the first and second differential inputs;
- a second pair of active loads coupled between said second differential pair and said second power source;
- a second current source coupled between said second differential pair and said first power source;
- a first complementary source follower coupled to a first node between the first of said first pair of the active loads and said first differential pair and coupled to a first node between the first of said second pair of the active loads and said second differential pair;
- and
- a second complementary source follower coupled to a second node between the second of said first pair of the active loads and said first differential pair and coupled to a second node between the second of said second pair of the active loads and said second differential pair.
A low voltage differential signaling circuit using complementary source coupled logic, said low voltage differential signaling circuit comprising:
- an n-type differential pair receiving first and second differential inputs;
- a first pair of active loads coupled between said n-type differential pair and a first power source;
- a first current source coupled between said n-type differential pair and a second power source;
- a p-type differential pair receiving the first and second differential inputs;
- a second pair of active loads coupled between said p-type differential pair and said second power source;
- a second current source coupled between said second differential pair and said first power source;
- a first complementary shared source follower coupled to a first node between the first of said first pair of the active loads and said n-type differential pair and coupled to a first node between the first of said second pair of the active loads and said p-type differential pair, said first source follower producing a first differential output at a first output node;
- and
- a second complementary source follower coupled to a second node between the second of the first pair of the active loads and said n-type differential pair and coupled to a second node between the second of the second pair of the active loads and said p-type differential pair, said second source follower producing a second differential output at a second output node.
In a low voltage differential signaling circuit including a first type differential pair and a pair of source followers, wherein a pair of complementary type differential pairs are provided and both receive a common differential input signal, and wherein said pair of source followers are complementary source followers that are shared by and coupled to the pair of complementary type differential pairs and wherein said pair of source followers together produce a differential output signal.
A low voltage differential signaling circuit, comprising a pair of complementary type differential pairs and a pair of complementary source followers,
- wherein said pair of complementary source followers that are shared by the pair of complementary type differential pairs, and
- wherein each of the complementary source followers includes a first type transistor and a second type transistor, and wherein the first type transistor operates as a current source for an active load for a second type transistor within each of the pair of complementary type differential pairs, and the second type transistor operates as a current source for an active load for a first type transistor within each of the pair of complementary type differential pairs.
Dependencies are inferred from the claim text.