Domino logic element realizing high speed dynamic logic circuit

A dynamic logic element comprising:

• a dynamic logic circuit portion producing an output signal in response to an input signal by performing a precharge operation and a discharge operation at a dynamic node;
• and
• a detecting circuit portion which stops said precharge operation at said dynamic node when a potential level of said dynamic node reaches a predetermined potential level, wherein said detecting circuit portion comprises:
• a MOS transistor of a first channel type which has a source terminal coupled to a power supply terminal, a gate terminal coupled to an output terminal of said dynamic logic element, and a drain terminal coupled to a dynamic node for retaining a precharge condition;
• and
• a MOS transistor of a second channel type which has a drain terminal coupled to said dynamic node for retaining a precharge condition, a gate terminal coupled to a clock input terminal of said dynamic logic element, and a source terminal coupled to the ground terminal, said second channel type being opposite to said first channel type;
• and
• wherein, in said detecting circuit portion, a current drive ability of said MOS transistor of a first channel type is larger than a current drive ability of said MOS transistor of a second channel type.

A domino logic circuit for use in a dynamic logic circuit, said domino logic circuit comprises:

• a plurality of domino logic elements which are coupled in tandem and in which a common clock signal is supplied to clock input terminals of said plurality of domino logic elements;
• wherein each of said domino logic elements comprises a detecting circuit portion which receives an output signal of said domino logic element fed back thereto, which detects completion of a precharge operation, and which, upon detection of completion of a precharge operation, finishes a precharge phase, wherein said detecting circuit portion in each of said domino logic elements comprises:
• a MOS transistor of a first channel type which has a source terminal coupled to a power supply terminal, a gate terminal coupled to an output terminal of said domino logic element, and a drain terminal coupled to a dynamic node for retaining a precharge condition;
• and
• a MOS transistor of a second channel type which has a drain terminal coupled to said dynamic node for retaining a precharge condition, a gate terminal coupled to a clock input terminal of said domino logic element, and a source terminal coupled to the ground terminal, said second channel type being opposite to said first channel type;
• and, wherein, among said plurality of domino logic elements coupled in tandem, said domino logic element at the most front stage comprises:
• a first channel type MOS transistor for precharging, a plurality of second channel type MOS transistors constituting a MOS logic network, a second channel type MOS transistor for discharging and an inverter element;
• wherein said first channel type MOS transistor for precharging has a source terminal coupled to a power supply terminal, a gate terminal coupled to said dynamic node for retaining a precharge condition, and a drain terminal coupled to a dynamic node for retaining an output signal;
• wherein a main current path of said MOS logic network is coupled between said dynamic node for retaining an output signal and a drain terminal of said second channel type MOS transistor for discharging;
• wherein a source terminal of said second channel type MOS transistor for discharging is coupled to the ground terminal, and a gate terminal of said second channel type MOS transistor is coupled to said dynamic node for retaining a precharge condition;
• wherein an input of said inverter element is coupled to said dynamic node for retaining an output signal, and an output of said inverter element is coupled to said output terminal;
• wherein, among said plurality of domino logic elements coupled in tandem, each of said domino logic elements at the second stage and the stage thereafter comprises a first channel type MOS transistors for precharging, a plurality of second channel type MOS transistor constituting a MOS logic network, and an inverter element;
• wherein said first channel type MOS transistor for precharging has a source terminal coupled to a power supply terminal, a gate terminal coupled to said dynamic node for retaining a precharge condition, and a drain terminal coupled to a dynamic node for retaining an output signal;
• wherein a main current path of said MOS logic network is coupled between said dynamic node for retaining an output signal and the ground terminal;
• and
• wherein an input of said inverter element is coupled to said dynamic node for retaining an output signal, and an output of said inverter element is coupled to said output terminal.

A domino logic circuit for use in a dynamic logic circuit, said domino logic circuit comprises:

• a plurality of domino logic elements which are coupled in tandem and in which a common clock signal is supplied to clock input terminals of said plurality of domino logic elements;
• wherein each of said domino logic elements comprises a detecting circuit portion which receives an output signal of said domino logic element fed back thereto, which detects completion of a precharge operation, and which, upon detection of completion of a precharge operation, finishes a precharge phase, wherein said detecting circuit portion in each of said domino logic elements comprises:
• a MOS transistor of a first channel type which has a source terminal coupled to a power supply terminal, a gate terminal coupled to an output terminal of said domino logic element, and a drain terminal coupled to a dynamic node for retaining a precharge condition;
• and
• a MOS transistor of a second channel type which has a drain terminal coupled to said dynamic node for retaining a precharge condition, a gate terminal coupled to a clock input terminal of said domino logic element, and a source terminal coupled to the ground terminal, said second channel type being opposite to said first channel type;
• and
• wherein each of all of said plurality of domino logic elements coupled in tandem comprises a first channel type MOS transistor for precharging, a plurality of second channel type MOS transistors constituting a MOS logic network, a second channel type MOS transistor for discharging and an inverter element;
• wherein said first channel type MOS transistor for precharging has a source terminal coupled to a power supply terminal, a gate terminal coupled to said dynamic node for retaining a precharge condition, and a drain terminal coupled to a dynamic node for retaining an output signal;
• wherein a main current path of said MOS logic network is coupled between said dynamic node for retaining an output signal and a drain terminal of said second channel type MOS transistor for discharging;
• wherein a source terminal of said second channel type MOS transistor for discharging is coupled to the ground terminal, and a gate terminal of said second channel type MOS transistor is coupled to said dynamic mode for retaining a precharge condition;
• and
• wherein an input of said inverter element is coupled to said dynamic node for retaining an output signal, and an output of said inverter element is coupled to said output terminal.

A dynamic logic circuit comprising:

• N domino logic circuits coupled in tandem, where N is a positive integer;
• wherein each of said domino logic circuits comprises a plurality of domino logic elements which are coupled in tandem and in which a common clock signal is supplied to clock input terminals of said plurality of domino logic elements in one domino logic circuit;
• wherein the phase of a clock signal inputted to a domino logic circuit lags behind the phase of clock signal inputted to a domino logic circuit at the preceding state by 360/N degrees;
• and
• wherein each of said domino logic elements constituting each of said domino logic circuits comprises a detecting circuit portion which receives an output signal of said domino logic element fed back thereto, which detects completion of a precharge operation, and which, upon detection of completion of a precharge operation, finishes a precharge phase, wherein adjacent domino logic circuits of said N domino logic circuits are coupled in tandem without interposing a buffer circuit therebetween, and wherein, in at least one of said domino logic circuits, among said plurality of domino logic elements coupled in tandem, said domino logic element at the most front stage comprises:
• a first channel type MOS transistor for precharging, a plurality of second channel type MOS transistors constituting a MOS logic network, a second channel type MOS transistor for discharging and an inverter element;
• wherein said first channel type MOS transistor for precharging has a source terminal coupled to a power supply terminal, a gate terminal coupled to a dynamic node for retaining a precharge condition, and a drain terminal coupled to dynamic node for retaining an output signal;
• wherein a main current path of said MOS logic network is coupled between said dynamic node for retaining an output signal and drain terminal of said second chamber type MOS transistor for discharging;
• wherein a source terminal of said second channel type MOS transistor for discharging is coupled to the ground terminal, and a gate terminal of said second channel type MOS transistor is coupled to said dynamic node for retaining a precharge condition;
• wherein an input of said inverter element is coupled to said dynamic node for retaining an output signal, and an output of said inverter element is coupled to said output terminal;
• wherein, in said at least one of said domino logic circuits, among said plurality of domino logic elements coupled in tandem, each of said domino logic elements at the second stage and the stage thereafter comprises a first channel type MOS transistor for precharging, a plurality of second channel type MOS transistors constituting a MOS logic network, and an inverter element;
• wherein said first channel type MOS transistor for precharging has a source terminal coupled to a power supply terminal, a gate terminal coupled to said dynamic node for retaining a precharge condition, and a drain terminal coupled to a dynamic node for retaining an output signal;
• wherein a main current path of said MOS logic network is coupled between said dynamic node for retaining an output signal and the ground terminal;
• and
• wherein an input of said inverter element is coupled to said dynamic node for retaining an output signal, and an output of said inverter element is coupled to said output terminal.