Non-latency affected contention prevention during scan-based test

A circuit, comprising:

• a path circuit gated by a CPC;
• and
• the CPC,
• wherein the CPC prevents contention in the path circuit during a scan-based test,
• wherein the CPC allows functional operation to occur without adversely affecting a functional operation timing, provided that a time skew between two input signals to the CPC is approximately less than a difference between a time delay associated with a scan-based test logic value and a time delay associated with a functional logic value,
• wherein the CPC comprises:
• a first plurality of parallel XNOR gates for comparing a first address and a second address,
• a first NOR gate in parallel with the first plurality of XNOR gates for determining if the first and second addresses are both enabled for writes,
• a first plurality of NAND gates coupled to the first plurality of XNOR gates and the first NOR gate, and
• an OR gate coupled to the first plurality of NAND gates, wherein the OR gate outputs a first signal indicating whether or not the first and second addresses will contend in the path circuit.

A method for preventing contention in a path circuit during a scan-based test, comprising the steps of:

• (a) providing a first and a second signal, wherein the first signal is to write to a first address, wherein the second signal is to write to a second address;
• (b) providing a static logical value during functional mode, wherein the time skew is approximately less than a difference between a time delay associated with a scan-based test logic value and a time delay associated with a functional logic value;
• (c) comparing the first address with the second address;
• (d) determining if the first and second addresses are enabled for writes;
• and
• (e) outputting a first signal with a contention state if the first and second addresses are identical and enabled for writes.