High-voltage level tolerant transistor circuit
AssigneeU.S. Philips Corporation
InventorsAnne Johan Annema, Godefridus Johannes Gertrudis Maria Geelen
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Abstract
A high-voltage level tolerant transistor circuit, comprising a plurality of cascoded transistors, including a first transistor (T1) operatively connected to a high-voltage level node (3) and a second transistor (T2) operatively connected to a low-voltage level node (2). The first transistor (T1) connects to a biasing circuit (8), such as a voltage level shifter, providing a variable biasing level (V1) relative to a voltage level (VH) at the high-voltage level node (3).
Claims15
A high-voltage level tolerant transistor circuit, comprising a plurality of cascoded transistors, including a first transistor operatively connecting to a high-voltage level node and a second transistor operatively connecting to a low-voltage level node, wherein said first transistor connects to a biasing circuit providing a variable biasing level, characterized in that said biasing circuit is arranged for providing a biasing level relative to a voltage level at said high-voltage level node, and wherein said biasing circuit comprises a voltage level shifter, said voltage level shifter being operative in response to said voltage level at said high-voltage level node.
Dependencies are inferred from the claim text.