Level conversion circuit
AssigneeNEC Corporation
InventorMasakazu Kurisu
Life of this patent
Estimating the term…
Abstract
A circuit for converting a negative ECL level to a positive CMOS level is formed by a level conversion circuit input terminal 4 for inputting a negative ECL level, a level shifter 5, one end of which is connected to the input terminal 4, a load 6 of the level shifter 5, one end of which is connected to the level shifter 5 and the other end of which is connected to a positive power supply VDD, and a positive ECL-CMOS level converter 7 for comparing a voltage that is level shifted by the level shifter 5 with a reference voltage Vref and converting to a CMOS level.
Claims4
A level conversion circuit for converting a negative ECL level to a positive CMOS level, comprising:
- a level conversion circuit input terminal for inputting said negative ECL level;
- a level shifter, one end of which is connected to said input terminal;
- a load for said level shifter, one end of which is connected to said level shifter and the other end of which is connected to a positive power supply;
- and
- a positive ECL-CMOS level converter, which compares a voltage that is level shifted by said level shifter with a reference voltage and converts to a CMOS level,
- wherein said level shifter comprises an nMOS transistor with a shorted gate electrode and drain electrode, and said load comprises a pMOS transistor, a gate electrode of which is connected to ground, and a source electrode of which is connected to said positive power supply.
A level conversion circuit for converting a negative ECL level to a positive CMOS level, comprising:
- a level conversion circuit input terminal for inputting said negative ECL level;
- a level shifter, one end of which is connected to said input terminal;
- a load for said level shifter, one end of which is connected to said level shifter and the other end of which is connected to a positive power supply;
- and
- a positive ECL-CMOS level converter, which compares a voltage that is level shifted by said level shifter with a reference voltage and converts to a CMOS level,
- wherein said level shifter comprises a PN junction diode, and said load comprises a pMOS transistor, a gate electrode of which is connected to ground, and a source electrode of which is connected to said positive power supply.
Dependencies are inferred from the claim text.